新一代SRAM写余量的重新定义及写余量监控电路

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696326

K. Takeda, H. Ikeda, Y. Hagihara, M. Nomura, H. Kobatake

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引用次数: 94

摘要

我们重新定义了写保证金，以便能够量化PVT变化和写保证金改进的影响。基于此定义的写余量监控电路在90nm CMOS工艺中实现。该电路可应用于SRAM电源电路，以提高写入余量

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Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit

We redefine write margin in order to be able to quantify the effect of both PVT variation and write-margin improvement. A write-margin monitoring circuit based on this definition is implemented in a 90nm CMOS process. This circuit can be applied to an SRAM power supply circuit to improve the write margin

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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