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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers最新文献

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A 10b 50MS/s pipelined ADC with opamp current reuse 一个10b50ms /s的流水线ADC与运放电流复用
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696119
S. Ryu, B. Song, K. Bacrania
{"title":"A 10b 50MS/s pipelined ADC with opamp current reuse","authors":"S. Ryu, B. Song, K. Bacrania","doi":"10.1109/ISSCC.2006.1696119","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696119","url":null,"abstract":"Power-saving techniques such as opamp current reuse and capacitive level shift reduce the power consumption of a 10b pipelined ADC to 220muW/MHz. A 50MS/S prototype in 0.18mum CMOS consumes 18mW (11mW for analog) at 1.8V and occupies 1.1times1.3mm2. The measured ENOB of the ADC is 9.2b (8.8b) for a 1MHz (20MHz) input","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127165341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs 用于调试纳米CMOS集成电路的信号完整性自检概念
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696283
V. Petrescu, Marcel J. M. Pelgrom, H. Veendrick, P. Pavithran, J. Wieling
{"title":"A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs","authors":"V. Petrescu, Marcel J. M. Pelgrom, H. Veendrick, P. Pavithran, J. Wieling","doi":"10.1109/ISSCC.2006.1696283","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696283","url":null,"abstract":"A fully integrated signal-integrity self-test concept is implemented in a 90nm CMOS process. The outputs of different analog monitors are locally converted to digital form and then transported through a test-compatible scan chain. The temperature monitor has 4b resolution. The supply-noise monitor detects 10ps-wide pulses of 20mV. The total area overhead is <0.1%","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127235020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS 低电压薄氧化物CMOS混合电压I/O的ESD保护
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696284
M. Ker, W. Chang, Chang-Tzu Wang, Wen-Yi Chen
{"title":"ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS","authors":"M. Ker, W. Chang, Chang-Tzu Wang, Wen-Yi Chen","doi":"10.1109/ISSCC.2006.1696284","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696284","url":null,"abstract":"An ESD protection design for 1.2V/2.5V mixed-voltage I/O interfaces is discussed. A high-voltage-tolerant power-rail ESD clamp circuit is used; it is realized with low-voltage devices in a 0.13mum CMOS process. The four-mode ESD stresses on the mixed-voltage I/O pad and the whole-chip pin-to-pin ESD protection can be discharged by the proposed ESD protection scheme","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123703520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 2.3GHz LC-tank CMOS VCO with optimal phase noise performance 具有最佳相位噪声性能的2.3GHz LC-tank CMOS压控振荡器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696108
P. Andreani, A. Fard
{"title":"A 2.3GHz LC-tank CMOS VCO with optimal phase noise performance","authors":"P. Andreani, A. Fard","doi":"10.1109/ISSCC.2006.1696108","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696108","url":null,"abstract":"The phase-noise theory and design of a differential CMOS LC-tank VCO with double switch pair is presented. A formula for the minimum achievable phase noise in the 1/f2 region is derived. The 2.15 to 2.35GHz 0.3mum CMOS VCO has a phase noise of -143.9dBc/Hz at 3MHz offset and draws 4mA from a 2.5V supply","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126974009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
Active 2nd-order intermodulation calibration for direct-conversion receivers 直接转换接收机的主动二阶互调校准
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696240
Minghui Chen, Yue Wu, M. F. Chang
{"title":"Active 2nd-order intermodulation calibration for direct-conversion receivers","authors":"Minghui Chen, Yue Wu, M. F. Chang","doi":"10.1109/ISSCC.2006.1696240","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696240","url":null,"abstract":"A temperature-compensated active IM2 calibration circuit for direct-conversion receivers is fabricated with a mixer in 0.25mum CMOS. A squaring circuit senses the RF signal and generates a calibration current to cancel mixer IM2 distortion. The loading effect and noise contribution are minimized by gain boosting. IIP2 is boosted >20dB to >80dBm in the IMT band. The calibration circuit draws 1.5mA","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116020358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers 基于两层SOI定时电路盖格模式雪崩光电二极管三维集成的激光雷达成像仪
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696163
B. Aull, J. Burns, Chenson Chen, B. Felton, Helen Hanson, C. Keast, J. Knecht, A. Loomis, M. Renzi, A. Soares, V. Suntharalingam, K. Warner, Deanna Wolfson, D. Yost, D. Young
{"title":"Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers","authors":"B. Aull, J. Burns, Chenson Chen, B. Felton, Helen Hanson, C. Keast, J. Knecht, A. Loomis, M. Renzi, A. Soares, V. Suntharalingam, K. Warner, Deanna Wolfson, D. Yost, D. Young","doi":"10.1109/ISSCC.2006.1696163","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696163","url":null,"abstract":"A 64times64 laser-radar (ladar) detector array with 50mum pixel size measures the arrival times of single photons using Geiger-mode avalanche photodiodes (APD). A 3-tier structure with active devices on each tier is used with 227 transistors, six 3D vias and an APD in each pixel. A 9b pseudorandom counter in the pixel measures time. Initial imagery shows 2ns time quantization","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116232604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 64
A 64B CPU Pair: Dual- and Single-Processor Chips 64B CPU对:双处理器和单处理器芯片
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696064
E. B. Cohen, N. Rohrer, P. Sandon, M. Canada, C. Lichtenau, M. Ringler, P. Kartschoke, R. Floyd, Jan Heaslip, M. Ross, Th. Pflueger, R. Hilgendorf, P. McCormick, G. Salem, J. Connor, S. Geissler, D. Thygesen
{"title":"A 64B CPU Pair: Dual- and Single-Processor Chips","authors":"E. B. Cohen, N. Rohrer, P. Sandon, M. Canada, C. Lichtenau, M. Ringler, P. Kartschoke, R. Floyd, Jan Heaslip, M. Ross, Th. Pflueger, R. Hilgendorf, P. McCormick, G. Salem, J. Connor, S. Geissler, D. Thygesen","doi":"10.1109/ISSCC.2006.1696064","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696064","url":null,"abstract":"Two Powertrade-architecture 64b microprocessor chips are fabricated in 90nm dual strained-silicon SOI technology. The dual-processor chip has split clock domains and power planes, 1 MB L2 cache per core and a shared processor interconnect bus. The single-processor chip shares the dual's basic core and cache design","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122372678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 10Gb/s CMOS AGC Amplifier with 35dB Dynamic Range for 10Gb Ethernet 10Gb/s CMOS AGC放大器，动态范围35dB，适用于10Gb以太网
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696269
Chih-Fan Liao, Shen-Iuan Liu
{"title":"A 10Gb/s CMOS AGC Amplifier with 35dB Dynamic Range for 10Gb Ethernet","authors":"Chih-Fan Liao, Shen-Iuan Liu","doi":"10.1109/ISSCC.2006.1696269","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696269","url":null,"abstract":"A 10Gb/s AGC amplifier is implemented in 0.18mum CMOS technology. The circuit uses a linear-in-dB controlled VGA with 58dB tuning range. For input swings from 18mV<sub>pp</sub> to 1V<sub>pp</sub>, the output swing is 430mV<sub>pp</sub> within +0.4 to -0.8dB variations. The measured dynamic range is 35dB with BER <10 <sup>-12</sup>. The AGC consumes 54mW from a 1.8V supply","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"376 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122656134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A 200dB Dynamic Range Iris-less CMOS Image Sensor with Lateral Overflow Integration Capacitor using Hybrid Voltage and Current Readout Operation 采用电压和电流混合读出操作的横向溢流集成电容的200dB动态范围无虹膜CMOS图像传感器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696161
N. Akahane, Rie Ryuzaki, S. Adachi, K. Mizobuchi, S. Sugawa
{"title":"A 200dB Dynamic Range Iris-less CMOS Image Sensor with Lateral Overflow Integration Capacitor using Hybrid Voltage and Current Readout Operation","authors":"N. Akahane, Rie Ryuzaki, S. Adachi, K. Mizobuchi, S. Sugawa","doi":"10.1109/ISSCC.2006.1696161","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696161","url":null,"abstract":"A 2.6times2.6mm<sup>2</sup> image sensor fabricated in 0.35mum 2P3M CMOS contains 64times64 pixels with 20times20mum<sup>2</sup> pixel size and has an extended dynamic range of over 200dB. This DR is equivalent to the incident light ranging from about 10<sup>-2</sup> to 10<sup>8</sup> lx with the lens iris fixed","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129929273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
On-chip image rejection in a low-if cmos receiver 低中频cmos接收器的片上图像抑制
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696239
Mohammad Hajirostam, K. Martin
{"title":"On-chip image rejection in a low-if cmos receiver","authors":"Mohammad Hajirostam, K. Martin","doi":"10.1109/ISSCC.2006.1696239","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696239","url":null,"abstract":"An adaptive image-reject mixer is realized in a 0.18mum CMOS technology. The circuit achieves high image-rejection ratios without off-chip filters in applications such as TV tuners. Test results show a 54dB image-rejection ratio in a low-IF receiver. The circuit consumes 75mW from a 1.8V supply and occupies 2.25mm2 including pads","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120955811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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