A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696283

V. Petrescu, Marcel J. M. Pelgrom, H. Veendrick, P. Pavithran, J. Wieling

引用次数: 18

Abstract

A fully integrated signal-integrity self-test concept is implemented in a 90nm CMOS process. The outputs of different analog monitors are locally converted to digital form and then transported through a test-compatible scan chain. The temperature monitor has 4b resolution. The supply-noise monitor detects 10ps-wide pulses of 20mV. The total area overhead is <0.1%

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用于调试纳米CMOS集成电路的信号完整性自检概念

在90纳米CMOS工艺中实现了完全集成的信号完整性自检概念。不同模拟监视器的输出在本地转换为数字形式，然后通过测试兼容的扫描链传输。温度监测器有4b分辨率。电源噪声监测器检测10ps宽20mV脉冲。总面积开销<0.1%

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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