A 64B CPU Pair: Dual- and Single-Processor Chips

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696064

E. B. Cohen, N. Rohrer, P. Sandon, M. Canada, C. Lichtenau, M. Ringler, P. Kartschoke, R. Floyd, Jan Heaslip, M. Ross, Th. Pflueger, R. Hilgendorf, P. McCormick, G. Salem, J. Connor, S. Geissler, D. Thygesen

引用次数: 9

Abstract

Two Powertrade-architecture 64b microprocessor chips are fabricated in 90nm dual strained-silicon SOI technology. The dual-processor chip has split clock domains and power planes, 1 MB L2 cache per core and a shared processor interconnect bus. The single-processor chip shares the dual's basic core and cache design

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64B CPU对:双处理器和单处理器芯片

两个powertrade架构64b微处理器芯片采用90nm双应变硅SOI技术制造。双处理器芯片具有分裂的时钟域和电源平面，每核1mb二级缓存和共享处理器互连总线。单处理器芯片共享双处理器的基本核心和缓存设计

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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