低电压薄氧化物CMOS混合电压I/O的ESD保护

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696284

M. Ker, W. Chang, Chang-Tzu Wang, Wen-Yi Chen

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引用次数: 15

摘要

讨论了1.2V/2.5V混合电压I/O接口的ESD保护设计。采用耐高压电源轨ESD钳位电路;它是在0.13 μ m CMOS工艺的低压器件上实现的。提出的ESD保护方案可以解除混合电压I/O板上的四模ESD应力和整个芯片的引脚对引脚ESD保护

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS

An ESD protection design for 1.2V/2.5V mixed-voltage I/O interfaces is discussed. A high-voltage-tolerant power-rail ESD clamp circuit is used; it is realized with low-voltage devices in a 0.13mum CMOS process. The four-mode ESD stresses on the mixed-voltage I/O pad and the whole-chip pin-to-pin ESD protection can be discharged by the proposed ESD protection scheme

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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