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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers最新文献

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A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache 双核多线程Xeon处理器，16MB L3缓存
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696062
S. Rusu, S. Tam, H. Muljono, D. Ayers, Jonathan Chang
{"title":"A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache","authors":"S. Rusu, S. Tam, H. Muljono, D. Ayers, Jonathan Chang","doi":"10.1109/ISSCC.2006.1696062","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696062","url":null,"abstract":"A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm2 die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"127 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114108278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 90
Power Distribution Measurements of the Dual Core PowerPC/sup TM/ 970MP Microprocessor 双核PowerPC/sup TM/ 970MP微处理器的功率分布测量
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696278
H. Hamann, A. Weger, J. Lacey, E. B. Cohen, Craig Atherton
{"title":"Power Distribution Measurements of the Dual Core PowerPC/sup TM/ 970MP Microprocessor","authors":"H. Hamann, A. Weger, J. Lacey, E. B. Cohen, Craig Atherton","doi":"10.1109/ISSCC.2006.1696278","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696278","url":null,"abstract":"Spatially-resolved imaging of microprocessor power (SIMP) is shown to be a critical tool for measuring temperature and power distributions of a microprocessor under full operating conditions. In this paper, the SIMP technique is applied to the dual-core PowerPCtrade 970MP microprocessor","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124166510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 64b adder using self-calibrating differential output prediction logic 采用自校准差分输出预测逻辑的64b加法器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696231
Kian Haur Chong, L. McMurchie, C. Sechen
{"title":"A 64b adder using self-calibrating differential output prediction logic","authors":"Kian Haur Chong, L. McMurchie, C. Sechen","doi":"10.1109/ISSCC.2006.1696231","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696231","url":null,"abstract":"A 64b adder based on self-calibrating differential output-prediction logic is fabricated in a 0.13mum 1.2V process. This aggressive dynamic logic circuit family is enhanced with self-calibrating local clock generation using dual-rail completion detection. It has a normalized worst-case delay of 238ps (3.9 FO4 inverter delays) and consumes 30pJ per operation, which is 1.8times faster and 2times lower in energy than previously published 64b adder results, which were based on domino logic","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125478252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution 一种用于DVD-16写入系统的锁相环，具有63个输出相位和32ps的分辨率
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696306
S. Dosho, S. Sakiyama, Noriaki Takeda, Y. Tokunaga, T. Morie
{"title":"A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution","authors":"S. Dosho, S. Sakiyama, Noriaki Takeda, Y. Tokunaga, T. Morie","doi":"10.1109/ISSCC.2006.1696306","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696306","url":null,"abstract":"A current-controlled oscillator (CCO) with 32ps phase resolution is realized by coupling ring oscillators in a 65nm CMOS process. A compact layout method achieves 36times46mum2 area and multiphase outputs whose timing errors are small. A CCO with 63 output phases is used in the PLL for a DVDtimes16 write system. The measured DNL of the output phases is within 1.0LSB at 490MHz","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130795596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Increasing Microprocessor Speed by Massive Application of On-Die High-K MIM Decoupling Capacitors 大量应用片上高k值MIM去耦电容器提高微处理器速度
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696280
H. Sánchez, B. Johnstone, Doug Roberts, Om Mandhana, B. Melnick, M. Celik, M. Baker, J. Hayden, B. Min, J. Edgerton, B. White
{"title":"Increasing Microprocessor Speed by Massive Application of On-Die High-K MIM Decoupling Capacitors","authors":"H. Sánchez, B. Johnstone, Doug Roberts, Om Mandhana, B. Melnick, M. Celik, M. Baker, J. Hayden, B. Min, J. Edgerton, B. White","doi":"10.1109/ISSCC.2006.1696280","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696280","url":null,"abstract":"A 90nm SOI microprocessor with massive application of high-k MIM decoupling capacitor modules is proven to increase the maximum frequency of the processor by close to 10%. Simulations predict reduced power supply noise leading to improvements in Fmax by close to the equivalent of a transistor node increase. Simulations of applying MIM decoupling capacitors to high-speed I/O and PLL circuits show that they can further enhance performance and area requirements for these critical circuits in advanced technologies","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"260 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130851076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A 60GHz transmitter with integrated antenna in 0.18/spl mu/m SiGe BiCMOS technology 采用0.18/spl mu/m SiGe BiCMOS技术的60GHz集成天线发射机
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696104
Chi-Hsueh Wang, Yi-Hsien Cho, Chin-Shen Lin, Huei Wang, Chun-Hsiung Chen, D. Niu, J. Yeh, Chwan-Ying Lee, J. Chern
{"title":"A 60GHz transmitter with integrated antenna in 0.18/spl mu/m SiGe BiCMOS technology","authors":"Chi-Hsueh Wang, Yi-Hsien Cho, Chin-Shen Lin, Huei Wang, Chun-Hsiung Chen, D. Niu, J. Yeh, Chwan-Ying Lee, J. Chern","doi":"10.1109/ISSCC.2006.1696104","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696104","url":null,"abstract":"A 60GHz SiGe HBT transmitter IC with integrated antenna in a standard-bulk 0.18mum SiGe BiCMOS process is reported. This chip is composed of a VCO, a sub-harmonic mixer, a PA, and a tapered-slot antenna, all with differential designs. The measured results show 15.8dBm output power and 20.2dB conversion gain with 281mWdc power consumption","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116373758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
A 20mw 3.24mm2 fully integrated gps radio for cell-phones 一个20兆瓦3.24平方毫米的完全集成的手机gps无线电
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696248
V. D. Torre, M. Conta, R. Chokkalingam, G. Cusmai, P. Rossi, F. Svelto
{"title":"A 20mw 3.24mm2 fully integrated gps radio for cell-phones","authors":"V. D. Torre, M. Conta, R. Chokkalingam, G. Cusmai, P. Rossi, F. Svelto","doi":"10.1109/ISSCC.2006.1696248","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696248","url":null,"abstract":"A GPS receiver that can coexist with cellular transceivers is implemented in a 0.18mum SiGe BiCMOS technology and occupies 3.24mm 2. The device integrates polyphase filters, VGA, ADCs, fractional-N synthesizer, LNA, and mixers, minimizing desensitization and reciprocal mixing. The receiver consumes 20mW from a 1.8V supply and has 1dB gain desensitization with a -8dBm 1.9GHz blocker","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121941792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation 用于SONET/SDH时钟生成的具有无命中开关的单片低带宽抖动清除锁相环
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696129
D. C. Wei, Yunteng Huang, B. Garlepp, J. Hein
{"title":"A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation","authors":"D. C. Wei, Yunteng Huang, B. Garlepp, J. Hein","doi":"10.1109/ISSCC.2006.1696129","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696129","url":null,"abstract":"A single-chip jitter-cleaning PLL with hitless switching is presented. By utilizing the mostly-digital phase build-out technique, the steady-state output phase step after switching is bounded within 200ps. At the loop bandwidth of 800Hz, the maximum output phase transient slope is <4.5ns/ms. The jitter generation is 0.8ps in the OC48 band and 0.4ps in OC192 band. The 16.32mm2 chip is fabricated in a 0.25mum standard CMOS process and consumes 350mW at 3.3V","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124116120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 1.1V 3.1-to-9.5GHz MB-OFDM UWB transceiver in 90nm CMOS 1.1V 3.1至9.5 ghz MB-OFDM UWB收发器，采用90nm CMOS
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696071
Akio Tanaka, H. Okada, H. Kodama, H. Ishikawa
{"title":"A 1.1V 3.1-to-9.5GHz MB-OFDM UWB transceiver in 90nm CMOS","authors":"Akio Tanaka, H. Okada, H. Kodama, H. Ishikawa","doi":"10.1109/ISSCC.2006.1696071","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696071","url":null,"abstract":"A 3.1-to-9.5GHz UWB transceiver is implemented in 90nm CMOS technology. It includes a 12-band synthesizer and wideband TX/RX chains operating from a 1.1V supply. The transceiver provides a TX0IP3 of 7.2 to 8.6dBm, an RX gain of 58 to 64dB, and a NF of 6.3 to 7.8dB across 12 bands","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125896980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Thyristor-Based Volatile Memory in Nano-Scale CMOS 基于晶闸管的纳米级CMOS挥发性存储器
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI: 10.1109/ISSCC.2006.1696327
R. Roy, F. Nemati, Ken Young, B. Bateman, Rajesh Chopra, Seong-ook Jung, Chiming Show, Hyun-jin Cho
{"title":"Thyristor-Based Volatile Memory in Nano-Scale CMOS","authors":"R. Roy, F. Nemati, Ken Young, B. Bateman, Rajesh Chopra, Seong-ook Jung, Chiming Show, Hyun-jin Cho","doi":"10.1109/ISSCC.2006.1696327","DOIUrl":"https://doi.org/10.1109/ISSCC.2006.1696327","url":null,"abstract":"A thyristor-based memory cell technology provides SRAM-like performance at 2times to 3times the density of conventional 6T SRAM. The technology is readily embedded into conventional nano-scale CMOS and scales into future SOI and FinFET technologies. A 19mm2 0.13mum 9Mb SOI test chip has a 0.562mum2 cell with a cell-R/W time <2ns","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129408557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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