基于晶闸管的纳米级CMOS挥发性存储器

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696327

R. Roy, F. Nemati, Ken Young, B. Bateman, Rajesh Chopra, Seong-ook Jung, Chiming Show, Hyun-jin Cho

{"title":"基于晶闸管的纳米级CMOS挥发性存储器","authors":"R. Roy, F. Nemati, Ken Young, B. Bateman, Rajesh Chopra, Seong-ook Jung, Chiming Show, Hyun-jin Cho","doi":"10.1109/ISSCC.2006.1696327","DOIUrl":null,"url":null,"abstract":"A thyristor-based memory cell technology provides SRAM-like performance at 2times to 3times the density of conventional 6T SRAM. The technology is readily embedded into conventional nano-scale CMOS and scales into future SOI and FinFET technologies. A 19mm2 0.13mum 9Mb SOI test chip has a 0.562mum2 cell with a cell-R/W time <2ns","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Thyristor-Based Volatile Memory in Nano-Scale CMOS\",\"authors\":\"R. Roy, F. Nemati, Ken Young, B. Bateman, Rajesh Chopra, Seong-ook Jung, Chiming Show, Hyun-jin Cho\",\"doi\":\"10.1109/ISSCC.2006.1696327\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A thyristor-based memory cell technology provides SRAM-like performance at 2times to 3times the density of conventional 6T SRAM. The technology is readily embedded into conventional nano-scale CMOS and scales into future SOI and FinFET technologies. A 19mm2 0.13mum 9Mb SOI test chip has a 0.562mum2 cell with a cell-R/W time <2ns\",\"PeriodicalId\":166617,\"journal\":{\"name\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2006.1696327\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2006.1696327","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 7

摘要

基于晶闸管的存储单元技术提供类似SRAM的性能，密度是传统6T SRAM的2到3倍。该技术很容易嵌入到传统的纳米级CMOS中，并扩展到未来的SOI和FinFET技术中。19mm2 0.13mum 9Mb SOI测试芯片具有0.562mum2 cell, cell- r /W时间<2ns

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Thyristor-Based Volatile Memory in Nano-Scale CMOS

A thyristor-based memory cell technology provides SRAM-like performance at 2times to 3times the density of conventional 6T SRAM. The technology is readily embedded into conventional nano-scale CMOS and scales into future SOI and FinFET technologies. A 19mm2 0.13mum 9Mb SOI test chip has a 0.562mum2 cell with a cell-R/W time <2ns

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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