双核多线程Xeon处理器，16MB L3缓存

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696062

S. Rusu, S. Tam, H. Muljono, D. Ayers, Jonathan Chang

{"title":"双核多线程Xeon处理器，16MB L3缓存","authors":"S. Rusu, S. Tam, H. Muljono, D. Ayers, Jonathan Chang","doi":"10.1109/ISSCC.2006.1696062","DOIUrl":null,"url":null,"abstract":"A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm2 die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes","PeriodicalId":166617,"journal":{"name":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","volume":"127 7","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"90","resultStr":"{\"title\":\"A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache\",\"authors\":\"S. Rusu, S. Tam, H. Muljono, D. Ayers, Jonathan Chang\",\"doi\":\"10.1109/ISSCC.2006.1696062\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm2 die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes\",\"PeriodicalId\":166617,\"journal\":{\"name\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"volume\":\"127 7\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"90\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2006.1696062\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2006.1696062","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 90

摘要

双核64b Xeonreg MP处理器采用65nm 8M工艺实现。435mm2的芯片有1.328亿个晶体管。每个核心有两个线程和一个统一的1MB二级缓存。16MB统一的16路集合关联L3缓存实现了睡眠和关闭泄漏减少模式

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A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache

A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm2 die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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