采用自校准差分输出预测逻辑的64b加法器

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696231

Kian Haur Chong, L. McMurchie, C. Sechen

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引用次数: 11

摘要

采用0.13 μ m 1.2V工艺制作了一种基于自校准差分输出预测逻辑的64b加法器。这种激进的动态逻辑电路家族通过使用双轨完井检测的自校准本地时钟生成来增强。它的归一化最坏情况延迟为238ps (3.9 FO4逆变器延迟)，每次操作消耗30pJ，比先前发布的基于domino逻辑的64b加法器结果快1.8倍，能耗低2倍

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A 64b adder using self-calibrating differential output prediction logic

A 64b adder based on self-calibrating differential output-prediction logic is fabricated in a 0.13mum 1.2V process. This aggressive dynamic logic circuit family is enhanced with self-calibrating local clock generation using dual-rail completion detection. It has a normalized worst-case delay of 238ps (3.9 FO4 inverter delays) and consumes 30pJ per operation, which is 1.8times faster and 2times lower in energy than previously published 64b adder results, which were based on domino logic

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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