A 64b adder using self-calibrating differential output prediction logic

Abstract

A 64b adder based on self-calibrating differential output-prediction logic is fabricated in a 0.13mum 1.2V process. This aggressive dynamic logic circuit family is enhanced with self-calibrating local clock generation using dual-rail completion detection. It has a normalized worst-case delay of 238ps (3.9 FO4 inverter delays) and consumes 30pJ per operation, which is 1.8times faster and 2times lower in energy than previously published 64b adder results, which were based on domino logic