A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation

Abstract

A single-chip jitter-cleaning PLL with hitless switching is presented. By utilizing the mostly-digital phase build-out technique, the steady-state output phase step after switching is bounded within 200ps. At the loop bandwidth of 800Hz, the maximum output phase transient slope is <4.5ns/ms. The jitter generation is 0.8ps in the OC48 band and 0.4ps in OC192 band. The 16.32mm2 chip is fabricated in a 0.25mum standard CMOS process and consumes 350mW at 3.3V