一个10b50ms /s的流水线ADC与运放电流复用

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696119

S. Ryu, B. Song, K. Bacrania

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引用次数: 23

摘要

诸如运放电流复用和电容电平移位等节能技术可将10b流水线ADC的功耗降低至220muW/MHz。在0.18mum CMOS中，50MS/S的原型在1.8V下消耗18mW(模拟11mW)，占地1.1 × 1.3mm2。对于1MHz (20MHz)输入，ADC的测量ENOB为9.2b (8.8b)

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A 10b 50MS/s pipelined ADC with opamp current reuse

Power-saving techniques such as opamp current reuse and capacitive level shift reduce the power consumption of a 10b pipelined ADC to 220muW/MHz. A 50MS/S prototype in 0.18mum CMOS consumes 18mW (11mW for analog) at 1.8V and occupies 1.1times1.3mm2. The measured ENOB of the ADC is 9.2b (8.8b) for a 1MHz (20MHz) input

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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