Y. Kanno, H. Mizuno, Y. Yasu, K. Hirose, Y. Shimazaki, T. Hoshi, Y. Miyairi, T. lshii, T. Yamada, T. Irita, T. Hattori, K. Yanagisawa, N. lrie
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Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor
Hierarchical power distribution using a power tree is developed. It supports fine-grained power gating with dozens of power domains like fine-grained clock gating and effectively reduces leakage currents for 1-million-gate power domains to 1/4000 in multi-CPU processors with minimal area overhead. This paper demonstrates the integration of 20 power domains in a 90nm single-chip 3G cellular phone processor
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