A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696055

Edoardo Prete, Dirk Scheideler, A. Sanders

引用次数: 32

Abstract

An architecture for next-generation memory interface is demonstrated using 90nm bulk silicon to provide a 2-tap emphasized TX with <19ps jitter at 9.6Gb/s. The circuit uses a programmable PLL to track jitter up to 200MHz. The transceiver consumes 100mW from a 1V supply

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用于下一代存储器接口的90nm CMOS 100mW 9.6Gb/s收发器

展示了一种使用90nm大块硅的下一代存储器接口架构，该架构可提供9.6Gb/s速度下抖动<19ps的2分路强化TX。该电路使用可编程锁相环来跟踪高达200MHz的抖动。收发器从1V电源中消耗100mW

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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