20Gb/s嵌入式时钟收发器在90nm CMOS

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696181

B. Casper, J. Jaussi, F. O’Mahony, M. Mansuri, K. Canagasaby, J. Kennedy, R. Mooney

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引用次数: 2

摘要

采用90nm CMOS的转发时钟I/O链路能够在7英寸FR4上以20Gb/s的速度传递数据，具有2个插座和封装，功耗低于12mW/Gb/s。采用无源分布和转发时钟的交流耦合实现820 fsrms的采样时间不确定性。超过-15dB的奈奎斯特速率信道损耗使用4分接发送均衡和接收器连续时间均衡的组合进行补偿

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A 20Gb/s Embedded Clock Transceiver in 90nm CMOS

A forwarded clock I/O link in 90nm CMOS is capable of passing data at 20Gb/s over 7-inches of FR4 with 2 sockets and packages at a power dissipation of less than 12mW/Gb/s. Passive distribution and AC coupling of the forwarded clock are used to achieve 820 fsrms of sample-time uncertainty. Nyquist rate channel losses in excess of -15dB are compensated using a combination of 4-tap transmit equalization and receiver continuous-time equalization

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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