A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90nm digital CMOS

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696120

Yasuhide Shimizu, Shigemitsu Murayama, Kohhei Kudoh, Hiroaki Yatsuda, Akihide Ogawa

引用次数: 19

Abstract

A 12b 40MS/s 2-step subranging ADC is realized in a 90nm digital CMOS process. It uses a 7b coarse quantizer with a high-gain offset-canceling positive-feedback amplifier. ENOB is 10.2b at a 0.7V supply and 11.0b at a 1.0V supply. The ADC consumes 30mW at 40MS/s

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一种30mW 12b 40MS/s带高增益抵消正反馈放大器的90nm数字CMOS分位ADC

采用90nm数字CMOS工艺实现了一个12b 40MS/s的两步分位ADC。它使用一个7b粗量化器和一个高增益抵消正反馈放大器。ENOB在0.7V电压下为102 b，在1.0V电压下为11.0b。ADC以40MS/s的速度消耗30mW

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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