耐pvt低1/f噪声双环混合锁相环，0.18/spl mu/m

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696304

Hyung-Rok Lee, Ook Kim, Keewook Jung, John Shin, D. Jeong

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引用次数: 6

摘要

具有小带宽数字环路和大带宽模拟环路的双环模数混合锁相环通过抑制1/f噪声实现低抖动，并且不需要片外环路滤波器组件。窄幅VCO的工作范围为10 ~ 200MHz。在此范围内的输出抖动<0.028UIpp。该芯片采用0.18 μ m CMOS工艺，从1.8V电源消耗50mW

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A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18/spl mu/m

A dual-loop analog-digital hybrid PLL with a small-bandwidth digital loop and large-bandwidth analog loop achieves low jitter by suppressing 1/f noise and does not require off-chip loop filter components. The operating range using a narrow-range VCO is from 10 to 200MHz. The output jitter over this range is <0.028UIpp. The chip is implemented in a 0.18mum CMOS process and consumes 50mW from a 1.8V supply

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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