用于芯片间时钟和数据链路的1Tb/s 3W电感耦合收发器

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696223

N. Miura, D. Mizoguchi, M. Inoue, K. Niitsu, Y. Nakagawa, M. Tago, M. Fukaishi, T. Sakurai, T. Kuroda

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引用次数: 61

摘要

一个1Tb/s的3W片间收发器，时钟速率为1GHz，每通道数据速率为1Gb/s，通过电感耦合传输时钟和数据。1024个数据收发器以30mum的间距布置。在0.18mum CMOS中，总布局面积为2mm2，芯片厚度为10mum。4相时分多址减少串扰，误码率<10 -;采用双相位调制提高了抗干扰性，降低了收发器的功耗

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A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link

A 1Tb/s 3W inter-chip transceiver transmits clock and data by inductive coupling at a clock rate of 1GHz and data rate of 1Gb/s per channel. 1024 data transceivers are arranged with a pitch of 30mum. The total layout area is 2mm2 in 0.18mum CMOS and the chip thickness is 10mum. 4-phase TDMA reduces crosstalk and the BER is <10minus;12. Bi-phase modulation is used to improve noise immunity, reducing power in the transceiver

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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