90nm CMOS中66GHz静态CML分频器的性能变化

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers Pub Date : 2006-09-18 DOI:10.1109/ISSCC.2006.1696274

J. Plouchart, Jonghae Kim, V. Karam, R. Trzcinski, J. Gross

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引用次数: 35

摘要

测量了90nm CMOS静态CML除以2，锁存器功耗为25.5mW的最大工作时钟频率为66GHz。统计自振荡频率测量在25℃和85℃时的平均值为42.6 ghz和39.2GHz，标准差为2.8GHz。1.4V时平均耗散功率为44.3mW，标准差为2.2mW

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Performance Variations of a 66GHz Static CML Divider in 90nm CMOS

A 66GHz maximum operating clock frequency is measured for a 90nm CMOS static CML divide-by-2 with a 25.5mW latch power dissipation. Statistical self-oscillation frequency measurements exhibit a mean of 42.6 and 39.2GHz at 25degC and 85degC, and a 2.8GHz standard deviation. The mean dissipated power is 44.3mW at 1.4V, with a 2.2mW standard deviation

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2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers

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