2016 IEEE Symposium on VLSI Technology最新文献_第8页

Production-worthy WOW 3D integration technology using bumpless interconnects and ultra-thinning processes 具有生产价值的WOW 3D集成技术，采用无凹凸互连和超薄工艺

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573427

T. Ohba

引用次数: 3

Overcoming scaling barriers through design technology CoOptimization 通过设计技术协同优化克服规模障碍

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573398

L. Liebmann, J. Zeng, Xuelian Zhu, Lei Yuan, G. Bouche, J. Kye

引用次数: 37

Circuit performance analysis of negative capacitance FinFETs 负电容finfet电路性能分析

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573446

S. Khandelwal, A. Khan, J. Duarte, A. Sachid, S. Salahuddin, C. Hu

引用次数: 39

Design / technology co-optimization of strain-induced layout effects in 14nm UTBB-FDSOI CMOS: Enablement and assessment of continuous-RX designs 14nm UTBB-FDSOI CMOS应变诱导布局效应的设计/技术协同优化:连续rx设计的实现和评估

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573425

R. Berthelon, F. Andrieu, E. Josse, R. Bingert, O. Weber, E. Serret, A. Aurand, S. DelMedico, V. Farys, C. Bernicot, E. Béchet, É. Bernard, T. Poiroux, D. Rideau, P. Scheer, E. Baylac, P. Perreau, M. Jaud, J. Lacord, E. Petitprez, A. Pofelski, S. Ortolland, P. Sardin, D. Dutartre, A. Claverie, M. Vinet, J. Marin, M. Haond

引用次数: 10

A 512×576 65-nm CMOS ISFET sensor for food safety screening with 123.8 mV/pH sensitivity and 0.01 pH resolution 用于食品安全筛选的512×576 65纳米CMOS ISFET传感器，灵敏度为123.8 mV/pH, pH分辨率为0.01

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573440

Yu Jiang, X. Liu, Tran Chien Dang, Mei Yan, Hao Yu, Jui-Cheng Huang, Cheng-Hsiang Hsieh, Tung-Tsun Chen

引用次数: 10

Smart solutions for efficient dual strain integration for future FDSOI generations 为未来FDSOI一代提供高效双应变集成的智能解决方案

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573406

A. Bonnevialle, C. Le Royer, Y. Morand, S. Reboh, C. Plantier, N. Rambal, J.-P Pedini, S. Kerdilès, P. Besson, J. Hartmann, D. Marseilhan, B. Mathieu, R. Berthelon, M. Cassé, F. Andrieu, D. Rouchon, O. Weber, F. Boeuf, M. Haond, A. Claverie, M. Vinet

引用次数: 1

Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing 与FinFET集成的四层3D垂直RRAM作为大脑启发认知信息处理的通用计算单元

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573431

Haitong Li, Kai-Shin Li, Chang-Hsien Lin, Juo-Luen Hsu, W. Chiu, Min-Cheng Chen, Tsung-Ta Wu, Joon Sohn, S. Eryilmaz, J. Shieh, W. Yeh, H.-S. Philip Wong

{"title":"Four-layer 3D vertical RRAM integrated with FinFET as a versatile computing unit for brain-inspired cognitive information processing","authors":"Haitong Li, Kai-Shin Li, Chang-Hsien Lin, Juo-Luen Hsu, W. Chiu, Min-Cheng Chen, Tsung-Ta Wu, Joon Sohn, S. Eryilmaz, J. Shieh, W. Yeh, H.-S. Philip Wong","doi":"10.1109/VLSIT.2016.7573431","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573431","url":null,"abstract":"For the first time, a four-layer HfOx-based 3D vertical RRAM, the “tallest” one ever reported, is developed and integrated with FinFET selector. Uniform memory performance across four layers is obtained (±0.8V switching, 106 endurance, 104s@125°C). SPICE simulations show that high drive current of pillar select transistors is required for high-rise 3D RRAM arrays. The four-layer 3D RRAM is a versatile computing unit for (a) brain-inspired computing and (b) in-memory computing. (a) Stochastic RRAM synapses enable robust pattern learning for a 3D neuromorphic visual system. The 3D architecture with dense and balanced neuron-synapse connections provides 55% EDP savings and 74% VDD reduction (enhanced robustness) compared with conventional 2D architecture; (b) in-memory logic such as NAND, NOR, and bit shift, are essential elements for hyper-dimensional computing. Utilizing the unique vertical connection of 3D RRAM cells, these operations are performed with little data movement.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125350056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 63

High aspect ratio InGaAs FinFETs with sub-20 nm fin width 高宽高比InGaAs finfet，翅片宽度低于20nm

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573408

A. Vardi, Jianqiang Lin, Wenjie Lu, Xin Zhao, J. D. del Alamo

引用次数: 10

Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells 无结栅全方位横向和垂直纳米线场效应管，简化处理，适用于高级逻辑和模拟/RF应用以及缩放SRAM单元

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573409

A. Veloso, B. Parvais, P. Matagne, E. Simoen, T. Huynh-Bao, V. Paraschiv, E. Vecchio, K. Devriendt, E. Rosseel, M. Ercken, B. Chan, C. Delvaux, E. Altamirano-Sanchez, J. Versluijs, Z. Tao, S. Suhard, S. Brus, A. Sibaja-Hernandez, N. Waldron, P. Lagrain, O. Richard, H. Bender, A. Chasin, B. Kaczer, T. Ivanov, S. Ramesh, K. De Meyer, J. Ryckaert, N. Collaert, A. Thean

{"title":"Junctionless gate-all-around lateral and vertical nanowire FETs with simplified processing for advanced logic and analog/RF applications and scaled SRAM cells","authors":"A. Veloso, B. Parvais, P. Matagne, E. Simoen, T. Huynh-Bao, V. Paraschiv, E. Vecchio, K. Devriendt, E. Rosseel, M. Ercken, B. Chan, C. Delvaux, E. Altamirano-Sanchez, J. Versluijs, Z. Tao, S. Suhard, S. Brus, A. Sibaja-Hernandez, N. Waldron, P. Lagrain, O. Richard, H. Bender, A. Chasin, B. Kaczer, T. Ivanov, S. Ramesh, K. De Meyer, J. Ryckaert, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2016.7573409","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573409","url":null,"abstract":"We report a comprehensive evaluation of junctionless (JL) vs. conventional inversion-mode (IM) gate-all-around (GAA) nanowire FETs (NWFETs) with the same lateral (L) configuration. Lower IOFF values and excellent electrostatics can be obtained with optimized NW doping for a given JL NW size (WNW≤25nm, HNW~22nm), with increased doping enabling ION improvement without IOFF penalty for WNW ≤10nm. These devices also appear as a viable option for analog/RF, showing similar speed and voltage gain, and reduced LF noise as compared to IM NWFETs. VT mismatch performance shows higher AVT with increased NW doping for JL NMOS, with less impact seen for PMOS and at smaller NWs. The JL concept is also demonstrated in vertical (V) GAA-NWFETs with in-situ doped Si epi NW pillars (dNW≥20-30nm), integrated on the same 300mm Si platform as lateral devices. Low IOFF, IG, and good electrostatics are achieved over a wide range of VNW arrays. Lastly, a novel SRAM design is proposed, taking advantage of the JL process simplicity, by vertically stacking two VNWFETs (n/n or p/p) to reduce SRAM area per bit by 39%.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125640388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

RTN-based defect tracking technique: Experimentally probing the spatial and energy profile of the critical filament region and its correlation with HfO2RRAM switching operation and failure mechanism 基于rtn的缺陷跟踪技术:实验探测临界灯丝区域的空间和能量分布及其与HfO2RRAM开关操作和失效机制的相关性

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573402

Chai Zheng, Jigang Ma, W. Zhang, B. Govoreanu, Eddy Simoen, J. Zhang, Z. Ji, Rui Gao, Guido Groeseneken, Malgorzata Jurczak

引用次数: 24