{"title":"具有生产价值的WOW 3D集成技术,采用无凹凸互连和超薄工艺","authors":"T. Ohba","doi":"10.1109/VLSIT.2016.7573427","DOIUrl":null,"url":null,"abstract":"Wafer-on-Wafer (WOW) technology for three-dimensional (3D) integration is discussed [1]. Back-to-face wafer stacking using bumpless interconnects and ultra-thinning of wafers are key features used as alternatives to conventional micro-bumps and chip-based stacking technologies [2]-[6]. There is no need for a bump process involving solder bumps and Cu posts for die-to-die internal electronic connections. Ultra-thinning of wafers down to ~2 μm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of through-silicon-vias (TSVs).","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Production-worthy WOW 3D integration technology using bumpless interconnects and ultra-thinning processes\",\"authors\":\"T. Ohba\",\"doi\":\"10.1109/VLSIT.2016.7573427\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Wafer-on-Wafer (WOW) technology for three-dimensional (3D) integration is discussed [1]. Back-to-face wafer stacking using bumpless interconnects and ultra-thinning of wafers are key features used as alternatives to conventional micro-bumps and chip-based stacking technologies [2]-[6]. There is no need for a bump process involving solder bumps and Cu posts for die-to-die internal electronic connections. Ultra-thinning of wafers down to ~2 μm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of through-silicon-vias (TSVs).\",\"PeriodicalId\":129300,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Technology\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2016.7573427\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573427","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Production-worthy WOW 3D integration technology using bumpless interconnects and ultra-thinning processes
Wafer-on-Wafer (WOW) technology for three-dimensional (3D) integration is discussed [1]. Back-to-face wafer stacking using bumpless interconnects and ultra-thinning of wafers are key features used as alternatives to conventional micro-bumps and chip-based stacking technologies [2]-[6]. There is no need for a bump process involving solder bumps and Cu posts for die-to-die internal electronic connections. Ultra-thinning of wafers down to ~2 μm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of through-silicon-vias (TSVs).