2016 IEEE Symposium on VLSI Technology

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2016 IEEE Symposium on VLSI Technology - 最新文献

MoS2 U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS2 availability

Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573375 Kai-Shin Li, Bo-Wei Wu, Lain‐Jong Li, Ming-Yang Li, Chia-Chin Cheng, Cho-Lun Hsu, Chang-Hsien Lin, Yi-Ju Chen, Chun-Chi Chen, C. Wu, Min-Cheng Chen, J. Shieh, W. Yeh, Y. Chueh, Fu-Liang Yang, C. Hu

Performance improvement of InxGa1−xAs Tunnel FETs with Quantum Well and EOT scaling

Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573443 D. Ahn, S. Ji, M. Takenaka, S. Takagi

Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D+IC

Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573448 Chih-Chao Yang, Kuan‐Chang Chiu, Cheng-Tse Chou, Chang-Ning Liao, Meng‐Hsi Chuang, Tung-Ying Hsieh, Wen-Hsien Huang, C. Shen, J. Shieh, W. Yeh, Yu-Hsiu Chen, Meng-Chyi Wu, Yi‐Hsien Lee

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