Kai-Shin Li, Bo-Wei Wu, Lain‐Jong Li, Ming-Yang Li, Chia-Chin Cheng, Cho-Lun Hsu, Chang-Hsien Lin, Yi-Ju Chen, Chun-Chi Chen, C. Wu, Min-Cheng Chen, J. Shieh, W. Yeh, Y. Chueh, Fu-Liang Yang, C. Hu
{"title":"MoS2 U-shape MOSFET with 10 nm channel length and poly-Si source/drain serving as seed for full wafer CVD MoS2 availability","authors":"Kai-Shin Li, Bo-Wei Wu, Lain‐Jong Li, Ming-Yang Li, Chia-Chin Cheng, Cho-Lun Hsu, Chang-Hsien Lin, Yi-Ju Chen, Chun-Chi Chen, C. Wu, Min-Cheng Chen, J. Shieh, W. Yeh, Y. Chueh, Fu-Liang Yang, C. Hu","doi":"10.1109/VLSIT.2016.7573375","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573375","url":null,"abstract":"A U-shape MoS2 pMOSFET with 10nm channel and poly-Si source/drain is demonstrated. The fabrication process is simple. Because the Si S/D serves as the nucleation seed for CVD MoS2 deposition, thin MoS2 is well deposited in the channel region any where over the fully scale oxide coated Si wafer. This is a big step forward toward a low cost multi-layer stacked TMD IC technology.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127162926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Performance improvement of InxGa1−xAs Tunnel FETs with Quantum Well and EOT scaling","authors":"D. Ahn, S. Ji, M. Takenaka, S. Takagi","doi":"10.1109/VLSIT.2016.7573443","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573443","url":null,"abstract":"In<sub>0.53</sub>Ga<sub>0.47</sub>As/In<sub>x</sub>Ga<sub>1-x</sub>As/In<sub>0.53</sub>Ga<sub>0.47</sub>As Quantum Well (QW) structure Tunnel FETs (TFETs) has been proposed and demonstrated. The systematic QW In content and thickness dependence on the TFET performance was quantitatively examined. The QW TFETs can significantly enhance the tunneling probability and resulting on-current (I<sub>on</sub>) by lower bandgap (E<sub>g</sub>) of the higher In content InGaAs than bulk In<sub>x</sub>Ga<sub>1-x</sub>As TFETs, while the increase in the off current (I<sub>off</sub>) can be suppressed by source junction formation in low In content In<sub>0.53</sub>Ga<sub>0.47</sub>As regions. The minimum sub-threshold swing (S.S.<sub>min</sub>) of 62 mV/dec was obtained at V<sub>D</sub>=150mV in the In<sub>0.53</sub>Ga<sub>0.47</sub>As/In<sub>x</sub>Ga<sub>1-x</sub>As (3nm)/In<sub>0.53</sub>Ga<sub>0.47</sub>As QW structure. Also, the highest I<sub>on</sub> of 56μA/μm at V<sub>D</sub>=1V among the fabricated InGaAs QW TFETs was obtained by In<sub>0.53</sub>Ga<sub>0.47</sub>As/InAs(5 nm)/In<sub>0.53</sub>Ga<sub>0.47</sub>As QW structure. We have also realized EOT-scaled bulk In<sub>0.53</sub>Ga<sub>0.47</sub>As TFETs with 1.7nm-CET HfO<sub>2</sub> (2.7nm)/Al<sub>2</sub>O<sub>3</sub> (0.3nm) gate stacks, exhibiting S.S<sub>min</sub> of 57 mV/dec at V<sub>D</sub>=100 mV.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129509889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chih-Chao Yang, Kuan‐Chang Chiu, Cheng-Tse Chou, Chang-Ning Liao, Meng‐Hsi Chuang, Tung-Ying Hsieh, Wen-Hsien Huang, C. Shen, J. Shieh, W. Yeh, Yu-Hsiu Chen, Meng-Chyi Wu, Yi‐Hsien Lee
{"title":"Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D+IC","authors":"Chih-Chao Yang, Kuan‐Chang Chiu, Cheng-Tse Chou, Chang-Ning Liao, Meng‐Hsi Chuang, Tung-Ying Hsieh, Wen-Hsien Huang, C. Shen, J. Shieh, W. Yeh, Yu-Hsiu Chen, Meng-Chyi Wu, Yi‐Hsien Lee","doi":"10.1109/VLSIT.2016.7573448","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573448","url":null,"abstract":"A monolithic 3D image sensor is demonstrated by sequentially fabricating large-area (>2cm×2cm) monolayer (<;1nm) transition metal dichalcogenide (TMD) phototransistor array on top of a 3D logic/memory hybrid 3D+IC connected by high density interconnect. The photocurrent of the monolayer MoS2 phototransistor shows a linear response to the incident laser power density and exhibits high responsivity (>20A/W). The bottom 3D stackable poly-Si nanowire FET, fabricated by low thermal budget process (Tsub<;400°C), represents steep subthreshold swing (<;120mV/dec.) and high driving current (>200uA/um). The low driving voltage 6T SRAM shows a static noise margin (SNM) of 150 mV at VDD=0.5V. Such integration of large-area monolayer TMD phototransistor array on logic/memory hybrid 3D+IC enables the low power and low cost monolithic 3D image sensor.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121580121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Frougier, N. Shukla, D. Deng, M. Jerry, Ahmedullah Aziz, L. Liu, G. Lavallee, T. Mayer, S. Gupta, S. Datta
{"title":"Phase-Transition-FET exhibiting steep switching slope of 8mV/decade and 36% enhanced ON current","authors":"J. Frougier, N. Shukla, D. Deng, M. Jerry, Ahmedullah Aziz, L. Liu, G. Lavallee, T. Mayer, S. Gupta, S. Datta","doi":"10.1109/VLSIT.2016.7573445","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573445","url":null,"abstract":"Vanadium dioxide (VO2), which exhibits electrically induced abrupt insulator-to-metal phase transition (IMT), is monolithically integrated with Silicon MOSFET to demonstrate a steep-slope (sub-kT/q) Phase-Transition FET (Phase-FET). The Phase-FET exhibits switching-slope (SS) of 8mV/decade leading to 36% increase in ON current (ION) over baseline MOSFET. We analyze the electrical characteristics of several threshold-switching materials with enhanced resistivity ratios (>105) beyond VO2 and harness them to enhance the performance of 14nm node FinFETs. Our analysis shows that up to 2.9× increase in ION, and 1.86× reduction in energy at (iso-delay) for an 11 stage ring oscillator (RO) is achievable with Phase FETs using Cu-doped HfO2 threshold switches.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128056039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Goux, A. Belmonte, U. Celano, J. Woo, S. Folkersma, C. Y. Chen, A. Redolfi, A. Fantini, R. Degraeve, S. Clima, W. Vandervorst, M. Jurczak
{"title":"Retention, disturb and variability improvements enabled by local chemical-potential tuning and controlled Hour-Glass filament shape in a novel WWO3Al2O3Cu CBRAM","authors":"L. Goux, A. Belmonte, U. Celano, J. Woo, S. Folkersma, C. Y. Chen, A. Redolfi, A. Fantini, R. Degraeve, S. Clima, W. Vandervorst, M. Jurczak","doi":"10.1109/VLSIT.2016.7573404","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573404","url":null,"abstract":"We optimize a novel WWO3Al2O3Cu CBRAM cell allowing excellent control of Hour-Glass (HG) shaped Conductive Filament (CF), improving switching variability, disturb and retention at low current. We evidence for the first time the critical impact of the Cu chemical potential close to the HG constriction on state retention.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125611638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Togo, W. Tong, X. Zhang, D. Triyoso, J. Lian, Y. M. Randriamihja, S. Uppal, S. Dag, E. C. Silva, M. Kota, T. Shimizu, S. Patil, M. Eller, S. Samavedam
{"title":"Novel N/PFET Vt control by TiN plasma nitridation for aggressive gate scaling","authors":"M. Togo, W. Tong, X. Zhang, D. Triyoso, J. Lian, Y. M. Randriamihja, S. Uppal, S. Dag, E. C. Silva, M. Kota, T. Shimizu, S. Patil, M. Eller, S. Samavedam","doi":"10.1109/VLSIT.2016.7573436","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573436","url":null,"abstract":"A novel N/PFET threshold voltage (Vt) control scheme was developed for aggressive gate scaling. TiN plasma nitridation reduces absolute Vt by 100mV for both NFETs and PFETs at the same time without photolithography step increase and performance or reliability penalty. TiN plasma nitridation does not need additional work function metal (WFM) to control Vt and hence allows thicker gate contact metal for low gate resistance and improved AC performance.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121724298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Ho, T. Shen, P. Hsu, S. Chang, S. Wen, M. Lin, P. Wang, S. Liao, C. Chou, K. M. Peng, C. M. Wu, W. Chang, Y. H. Chen, F. Chen, L. W. Lin, T. Tsai, S. F. Lim, C. J. Yang, M. Shieh, H. Liao, C. H. Lin, P. Pai, T. Chan, Y. Chiao
{"title":"Random soft error suppression by stoichiometric engineering: CMOS compatible and reliable 1Mb HfO2-ReRAM with 2 extra masks for embedded IoT systems","authors":"C. Ho, T. Shen, P. Hsu, S. Chang, S. Wen, M. Lin, P. Wang, S. Liao, C. Chou, K. M. Peng, C. M. Wu, W. Chang, Y. H. Chen, F. Chen, L. W. Lin, T. Tsai, S. F. Lim, C. J. Yang, M. Shieh, H. Liao, C. H. Lin, P. Pai, T. Chan, Y. Chiao","doi":"10.1109/VLSIT.2016.7573366","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573366","url":null,"abstract":"12\" manufacturable 90nm CMOS fully compatible 1Mb HfO2-ReRAM by 2 extra masks between Metals with BEoL thermal stress immunity is for the first time achieved in this work. Cycle random soft error, for the first time systematically observed in this work, due to improper phase-transition of TiOδ on filament are successfully suppressed by stoichiometric engineering on HfO2 / reservoir interface to achieve reliable 20K / 100K endurance and 85°C 10 years retention. This technology can thus offer potential applications of embedded IoT systems due to low energy consumption and cost effective benefit.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131487127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Pasini, P. Batude, J. Lacord, M. Cassé, B. Mathieu, B. Sklénard, F. P. Luce, J. Micout, A. Payet, F. Mazen, P. Besson, E. Ghegin, J. Borrel, R. Daubriac, L. Hutin, D. Blachier, D. Barge, S. Chhun, V. Mazzocchi, A. Cros, J. Barnes, Z. Saghi, V. Delaye, N. Rambal, V. Lapras, J. Mazurier, O. Weber, F. Andrieu, L. Brunet, C. Fenouillet-Béranger, Q. Rafhay, G. Ghibaudo, F. Cristiano, M. Haond, F. Boeuf, M. Vinet
{"title":"High performance CMOS FDSOI devices activated at low temperature","authors":"L. Pasini, P. Batude, J. Lacord, M. Cassé, B. Mathieu, B. Sklénard, F. P. Luce, J. Micout, A. Payet, F. Mazen, P. Besson, E. Ghegin, J. Borrel, R. Daubriac, L. Hutin, D. Blachier, D. Barge, S. Chhun, V. Mazzocchi, A. Cros, J. Barnes, Z. Saghi, V. Delaye, N. Rambal, V. Lapras, J. Mazurier, O. Weber, F. Andrieu, L. Brunet, C. Fenouillet-Béranger, Q. Rafhay, G. Ghibaudo, F. Cristiano, M. Haond, F. Boeuf, M. Vinet","doi":"10.1109/VLSIT.2016.7573407","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573407","url":null,"abstract":"3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128929981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Franco, A. Vais, S. Sioncke, V. Putcha, B. Kaczer, B. Shie, X. Shi, R. Mahlouji, L. Nyns, D. Zhou, N. Waldron, J. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, H. Arimura, T. Schram, L. Ragnarsson, A. Sibaja Hernandez, G. Hellings, N. Horiguchi, M. Heyns, G. Groeseneken, D. Linten, N. Collaert, A. Thean
{"title":"Demonstration of an InGaAs gate stack with sufficient PBTI reliability by thermal budget optimization, nitridation, high-k material choice, and interface dipole","authors":"J. Franco, A. Vais, S. Sioncke, V. Putcha, B. Kaczer, B. Shie, X. Shi, R. Mahlouji, L. Nyns, D. Zhou, N. Waldron, J. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, H. Arimura, T. Schram, L. Ragnarsson, A. Sibaja Hernandez, G. Hellings, N. Horiguchi, M. Heyns, G. Groeseneken, D. Linten, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2016.7573371","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573371","url":null,"abstract":"We have shown that the poor PBTI reliability of IIIV/high-k gate stacks is universally related to process thermal budget limitations. Low temperature anneal optimization and high-k nitridation reduce oxide defect density. In contrast to a wide distribution of defect levels in Al2O3, HfO2 on InGaAs shows a minimum defect density ~0.2eV below the channel EC. By introducing an interface dipole, a significant reliability boost was demonstrated. While low thermal budget high-k quality and IIIV interface thermal stability constitute challenges, our results show that a reliable IIIV/high-k gate stack can be fabricated.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123576895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Application of CVS and VRS method for correlation of logic CMOS wear out to discrete device degradation based on ring oscillator circuits","authors":"A. Kerber, T. Nigam","doi":"10.1109/VLSIT.2016.7573372","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573372","url":null,"abstract":"Device level reliability margins are reducing for advanced MG/HK technology nodes, hence it is essential to comprehend product level reliability margin using CMOS circuits like ring oscillators (RO). In this paper we explore RO degradation for both bias temperature instability (BTI) and dielectric breakdown (DB). For BTI we demonstrate frequency independence up to ~3GHz. The observed AC relief is critical for determination of product reliability margin. In addition, we demonstrate for the first time Poisson scaling of dielectric breakdown in logic CMOS circuits confirming applicability of device level TDDB scaling models for product failure rate assessments.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125895577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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