Application of CVS and VRS method for correlation of logic CMOS wear out to discrete device degradation based on ring oscillator circuits

Abstract

Device level reliability margins are reducing for advanced MG/HK technology nodes, hence it is essential to comprehend product level reliability margin using CMOS circuits like ring oscillators (RO). In this paper we explore RO degradation for both bias temperature instability (BTI) and dielectric breakdown (DB). For BTI we demonstrate frequency independence up to ~3GHz. The observed AC relief is critical for determination of product reliability margin. In addition, we demonstrate for the first time Poisson scaling of dielectric breakdown in logic CMOS circuits confirming applicability of device level TDDB scaling models for product failure rate assessments.