Chih-Chao Yang, Kuan‐Chang Chiu, Cheng-Tse Chou, Chang-Ning Liao, Meng‐Hsi Chuang, Tung-Ying Hsieh, Wen-Hsien Huang, C. Shen, J. Shieh, W. Yeh, Yu-Hsiu Chen, Meng-Chyi Wu, Yi‐Hsien Lee
{"title":"采用大面积单层过渡金属二硫化物和逻辑/存储混合3D+IC实现单片3D图像传感器","authors":"Chih-Chao Yang, Kuan‐Chang Chiu, Cheng-Tse Chou, Chang-Ning Liao, Meng‐Hsi Chuang, Tung-Ying Hsieh, Wen-Hsien Huang, C. Shen, J. Shieh, W. Yeh, Yu-Hsiu Chen, Meng-Chyi Wu, Yi‐Hsien Lee","doi":"10.1109/VLSIT.2016.7573448","DOIUrl":null,"url":null,"abstract":"A monolithic 3D image sensor is demonstrated by sequentially fabricating large-area (>2cm×2cm) monolayer (<;1nm) transition metal dichalcogenide (TMD) phototransistor array on top of a 3D logic/memory hybrid 3D+IC connected by high density interconnect. The photocurrent of the monolayer MoS2 phototransistor shows a linear response to the incident laser power density and exhibits high responsivity (>20A/W). The bottom 3D stackable poly-Si nanowire FET, fabricated by low thermal budget process (Tsub<;400°C), represents steep subthreshold swing (<;120mV/dec.) and high driving current (>200uA/um). The low driving voltage 6T SRAM shows a static noise margin (SNM) of 150 mV at VDD=0.5V. Such integration of large-area monolayer TMD phototransistor array on logic/memory hybrid 3D+IC enables the low power and low cost monolithic 3D image sensor.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D+IC\",\"authors\":\"Chih-Chao Yang, Kuan‐Chang Chiu, Cheng-Tse Chou, Chang-Ning Liao, Meng‐Hsi Chuang, Tung-Ying Hsieh, Wen-Hsien Huang, C. Shen, J. Shieh, W. Yeh, Yu-Hsiu Chen, Meng-Chyi Wu, Yi‐Hsien Lee\",\"doi\":\"10.1109/VLSIT.2016.7573448\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A monolithic 3D image sensor is demonstrated by sequentially fabricating large-area (>2cm×2cm) monolayer (<;1nm) transition metal dichalcogenide (TMD) phototransistor array on top of a 3D logic/memory hybrid 3D+IC connected by high density interconnect. The photocurrent of the monolayer MoS2 phototransistor shows a linear response to the incident laser power density and exhibits high responsivity (>20A/W). The bottom 3D stackable poly-Si nanowire FET, fabricated by low thermal budget process (Tsub<;400°C), represents steep subthreshold swing (<;120mV/dec.) and high driving current (>200uA/um). The low driving voltage 6T SRAM shows a static noise margin (SNM) of 150 mV at VDD=0.5V. Such integration of large-area monolayer TMD phototransistor array on logic/memory hybrid 3D+IC enables the low power and low cost monolithic 3D image sensor.\",\"PeriodicalId\":129300,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Technology\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2016.7573448\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573448","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Enabling monolithic 3D image sensor using large-area monolayer transition metal dichalcogenide and logic/memory hybrid 3D+IC
A monolithic 3D image sensor is demonstrated by sequentially fabricating large-area (>2cm×2cm) monolayer (<;1nm) transition metal dichalcogenide (TMD) phototransistor array on top of a 3D logic/memory hybrid 3D+IC connected by high density interconnect. The photocurrent of the monolayer MoS2 phototransistor shows a linear response to the incident laser power density and exhibits high responsivity (>20A/W). The bottom 3D stackable poly-Si nanowire FET, fabricated by low thermal budget process (Tsub<;400°C), represents steep subthreshold swing (<;120mV/dec.) and high driving current (>200uA/um). The low driving voltage 6T SRAM shows a static noise margin (SNM) of 150 mV at VDD=0.5V. Such integration of large-area monolayer TMD phototransistor array on logic/memory hybrid 3D+IC enables the low power and low cost monolithic 3D image sensor.