Demonstration of an InGaAs gate stack with sufficient PBTI reliability by thermal budget optimization, nitridation, high-k material choice, and interface dipole
J. Franco, A. Vais, S. Sioncke, V. Putcha, B. Kaczer, B. Shie, X. Shi, R. Mahlouji, L. Nyns, D. Zhou, N. Waldron, J. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, H. Arimura, T. Schram, L. Ragnarsson, A. Sibaja Hernandez, G. Hellings, N. Horiguchi, M. Heyns, G. Groeseneken, D. Linten, N. Collaert, A. Thean
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引用次数: 14
Abstract
We have shown that the poor PBTI reliability of IIIV/high-k gate stacks is universally related to process thermal budget limitations. Low temperature anneal optimization and high-k nitridation reduce oxide defect density. In contrast to a wide distribution of defect levels in Al2O3, HfO2 on InGaAs shows a minimum defect density ~0.2eV below the channel EC. By introducing an interface dipole, a significant reliability boost was demonstrated. While low thermal budget high-k quality and IIIV interface thermal stability constitute challenges, our results show that a reliable IIIV/high-k gate stack can be fabricated.