2016 IEEE Symposium on VLSI Technology最新文献_第2页

A Monte Carlo simulation method to predict large-density NAND product memory window from small-array test element group (TEG) verified on a 3D NAND Flash test chip 基于小阵列测试元件组(TEG)预测大密度NAND产品存储窗口的蒙特卡罗模拟方法在3D NAND闪存测试芯片上得到验证

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573386

C. Hsieh, H. Lue, T. Hsu, P. Du, K. Chiang, Chih-Yuan Lu

{"title":"A Monte Carlo simulation method to predict large-density NAND product memory window from small-array test element group (TEG) verified on a 3D NAND Flash test chip","authors":"C. Hsieh, H. Lue, T. Hsu, P. Du, K. Chiang, Chih-Yuan Lu","doi":"10.1109/VLSIT.2016.7573386","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573386","url":null,"abstract":"We developed a Monte Carlo simulation method to accurately predict the large-density NAND flash product memory window based on several device parameters collected in the small-array test element group (TEG). The required parameters include the ISPP slope, intrinsic Vt distribution sigma, program noise, random telegraph noise (RTN), and various interference ratios. All these parameters can be collected from the wafer acceptance test (WAT) of a small-array TEG. The simulation methodology is to randomly generate a Vt distribution ensemble that resembles the product memory cell. Programming simulation of each memory cell considers the programming distribution and various fluctuation factors during ISPP programming and verification. Experimental data of a fabricated 3D NAND test chip are compared with the simulation results, and show excellent consistency. This novel methodology not only provides memory product window from device parameters of TEG, but also emulates various MLC programming algorithms to optimize the product-level memory window.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133010773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Germanium-Tin heterojunction phototransistor: Towards high-efficiency low-power photodetection in short-wave infrared range 锗锡异质结光电晶体管:迈向短波红外高效低功耗光电探测

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573449

Wei Wang, Yuan Dong, S. Lee, W. Loke, X. Gong, S. Yoon, G. Liang, Y. Yeo

引用次数: 3

200–280GHz CMOS RF front-end of transmitter for rotational spectroscopy 旋转光谱发射机200-280GHz CMOS射频前端

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573400

N. Sharma, Q. Zhong, Z. Chen, W. Choi, J. P. McMillan, C. Neese, R. Schueler, I. Medvedev, F. D. De Lucia, K. O

引用次数: 30

Enabling high-performance heterogeneous TFET/CMOS logic with novel circuits using TFET unidirectionality and low-VDD operation 利用TFET单向性和低vdd操作的新颖电路实现高性能异构TFET/CMOS逻辑

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573442

D. Morris, Kaushik Vaidyanathan, U. Avci, Huichu Liu, T. Karnik, I. Young

{"title":"Enabling high-performance heterogeneous TFET/CMOS logic with novel circuits using TFET unidirectionality and low-VDD operation","authors":"D. Morris, Kaushik Vaidyanathan, U. Avci, Huichu Liu, T. Karnik, I. Young","doi":"10.1109/VLSIT.2016.7573442","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573442","url":null,"abstract":"Tunneling FETs (TFETs) offer better low-VDD performance than CMOS but lack performance above 0.5V VDD due to low drive current and VDD-dependent parasitic leakages. At low-VDD, TFET's higher energy efficiency enables 2X parallel performance for power constrained systems. For applications less amenable to parallelization, newly proposed circuits improve energy/op, performance and area by not only using TFET's steep sub-threshold swing, but also utilizing its asymmetric IDS-VDS characteristic. Design synthesis with sub-5nm node TFETs, MOSFETs and interconnects is used to assess trade-offs in industry logic blocks. In addition to a 44% energy reduction over CMOS circuits, novel TFET circuits improve dynamic energy by 32% and performance by 13% at logic cell level (4% and 10% respectively at synthesized logic block). Even with these benefits, single-threaded CPUs require CMOS logic's high performance. In this case, heterogeneous TFET/CMOS logic with low-overhead level-shifters improves performance 50% while reducing energy 42% for non-critical performance logic.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114054302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

High performance In0.53Ga0.47As FinFETs fabricated on 300 mm Si substrate 在300 mm Si衬底上制备的高性能In0.53Ga0.47As finfet

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573361

M. Huang, S. W. Chang, M. Chen, Y. Oniki, H. C. Chen, W. Lee, C. H. Lin, M. A. Khaderbad, K. Y. Lee, Z. Chen, P. Tsai, L. T. Lin, M. Tsai, C. Hung, T. C. Huang, Y. Lin, Y. Yeo, S. Jang, H. Hwang, H. Wang, Carlos H. Díaz

引用次数: 20

Comprehensive evaluation of early retention (fast charge loss within a few seconds) characteristics in tube-type 3-D NAND flash memory 管型3-D NAND闪存早期保留(几秒内快速电荷损失)特性的综合评价

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573385

Bongsik Choi, S. H. Jang, J. Yoon, Juhee Lee, M. Jeon, Yongwoo Lee, Jungmin Han, Jieun Lee, D. M. Kim, D. Kim, Chan Lim, Sungkye Park, Sung-Jin Choi

引用次数: 54

Smart power technologies enabling power SOC and SIP 智能电源技术，支持电源SOC和SIP

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573394

S. Pendharkar

引用次数: 5

Analog/RF wonderland: Circuit and technology co-optimization in advanced FinFET technology 模拟/射频仙境:先进FinFET技术中的电路和技术协同优化

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573399

F. Hsueh, Y. Peng, Chung-Hui Chen, T. Yeh, H. Hsieh, Chin-Ho Chang, Szu-Lin Liu, Mei-Chen Chuang, Mark Chen

引用次数: 7

Novel RRAM-enabled 1T1R synapse capable of low-power STDP via burst-mode communication and real-time unsupervised machine learning 通过突发模式通信和实时无监督机器学习实现低功耗STDP的新型rram启用1T1R突触

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573432

S. Ambrogio, S. Balatti, V. Milo, R. Carboni, Z. Wang, A. Calderoni, N. Ramaswamy, D. Ielmini

引用次数: 32

Advanced a-VMCO resistive switching memory through inner interface engineering with wide (>102) on/off window, tunable μA-range switching current and excellent variability 先进的a-VMCO阻性开关存储器通过内部接口工程，具有宽(>102)开/关窗口，μ a范围开关电流可调和优异的可变性

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573387

B. Govoreanu, L. D. Piazza, J. Ma, Thierry Conard, A. Vanleenhove, A. Belmonte, D. Radisic, M. Popovici, A. Velea, A. Redolfi, O. Richard, S. Clima, C. Adelmann, Hugo Bender, Malgorzata Jurczak

引用次数: 21