A Monte Carlo simulation method to predict large-density NAND product memory window from small-array test element group (TEG) verified on a 3D NAND Flash test chip

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI:10.1109/VLSIT.2016.7573386

C. Hsieh, H. Lue, T. Hsu, P. Du, K. Chiang, Chih-Yuan Lu

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引用次数: 15

Abstract

We developed a Monte Carlo simulation method to accurately predict the large-density NAND flash product memory window based on several device parameters collected in the small-array test element group (TEG). The required parameters include the ISPP slope, intrinsic Vt distribution sigma, program noise, random telegraph noise (RTN), and various interference ratios. All these parameters can be collected from the wafer acceptance test (WAT) of a small-array TEG. The simulation methodology is to randomly generate a Vt distribution ensemble that resembles the product memory cell. Programming simulation of each memory cell considers the programming distribution and various fluctuation factors during ISPP programming and verification. Experimental data of a fabricated 3D NAND test chip are compared with the simulation results, and show excellent consistency. This novel methodology not only provides memory product window from device parameters of TEG, but also emulates various MLC programming algorithms to optimize the product-level memory window.

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基于小阵列测试元件组(TEG)预测大密度NAND产品存储窗口的蒙特卡罗模拟方法在3D NAND闪存测试芯片上得到验证

基于小阵列测试元件组(TEG)中收集的多个器件参数，提出了一种蒙特卡罗模拟方法来准确预测大密度NAND闪存产品的存储窗口。所需参数包括ISPP斜率、固有Vt分布σ、程序噪声、随机电报噪声(RTN)和各种干扰比。所有这些参数都可以从小阵列TEG的晶圆验收测试(WAT)中得到。仿真方法是随机生成一个类似于产品存储单元的Vt分布集合。每个存储单元的编程仿真考虑了ISPP编程和验证过程中的编程分布和各种波动因素。将自制的三维NAND测试芯片的实验数据与仿真结果进行了比较，结果显示出良好的一致性。该方法不仅提供了TEG器件参数的存储器产品窗口，而且模拟了各种MLC编程算法来优化产品级存储器窗口。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 IEEE Symposium on VLSI Technology

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