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2016 IEEE Symposium on VLSI Technology最新文献

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Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling 完全兼容CMOS的3D垂直RRAM，具有自对准自选择单元，可实现低于5nm的缩放
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573388
Xiaoxin Xu, Q. Luo, Tiancheng Gong, L. Hangbing, S. Long, Qi Liu, S. Chung, Jing Li, Ming Liu
{"title":"Fully CMOS compatible 3D vertical RRAM with self-aligned self-selective cell enabling sub-5nm scaling","authors":"Xiaoxin Xu, Q. Luo, Tiancheng Gong, L. Hangbing, S. Long, Qi Liu, S. Chung, Jing Li, Ming Liu","doi":"10.1109/VLSIT.2016.7573388","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573388","url":null,"abstract":"In low cost vertical resistive switching memory (VRRAM), the inter-layer leakage becomes a serious problem, primarily resulting from the ultimate scaling in the vertical dimension. In this work, for the first time, we present a novel approach of fabricating 3D VRRAM using self-aligned self-selective RRAM to effectively address such challenge. By successfully suppressing the inter-layer leakage, the scaling limit of VRRAM could be extended beyond 5 nm. Other benefits, such as high nonlinearity (>103), low power consumption (sub-μA), robust endurance and excellent disturbance immunity, were also demonstrated.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123449184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Complete extraction of defect bands responsible for instabilities in n and pFinFETs 完整地提取了导致n和pfinfet不稳定的缺陷带
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573437
G. Rzepa, M. Waltl, W. Goes, B. Kaczer, J. Franco, T. Chiarella, N. Horiguchi, T. Grasser
{"title":"Complete extraction of defect bands responsible for instabilities in n and pFinFETs","authors":"G. Rzepa, M. Waltl, W. Goes, B. Kaczer, J. Franco, T. Chiarella, N. Horiguchi, T. Grasser","doi":"10.1109/VLSIT.2016.7573437","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573437","url":null,"abstract":"Bias temperature instabilities (BTI) are serious reliability issues in high-k technologies and occur for positive and negative stress voltages in both n and pMOSFETs. The cases with the strongest degradation, namely negative BTI (NBTI) in pMOS and positive BTI (PBTI) in nMOSFETs, are typically studied and modeled separately, which led to considerable inconsistencies regarding the distributions of the responsible defects. Here we present the first study which successfully describes all four combinations of BTI in n/pMOSFETs within a single model. This was achieved by determining the physical properties of the defects in HfO2 and in SiO2. Using our extraction method, any ambiguity regarding the location of the defect bands is completely eliminated, allowing for correct physics-based extrapolation of degradation data to use conditions.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127990745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 33
Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes 超低NMOS接触电阻率，采用新型等离子体DSS植入和激光退火后7 nm节点
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573383
C. Ni, K. V. Rao, F. Khaja, S. Sharma, S. Tang, J. J. Chen, K. Hollar, N. Breil, X. Li, M. Jin, C. Lazik, J. Lee, H. Maynard, N. Variam, A. Mayur, S. Kim, H. Chung, M. Chudzik, R. Hung, N. Yoshida, N. Kim
{"title":"Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes","authors":"C. Ni, K. V. Rao, F. Khaja, S. Sharma, S. Tang, J. J. Chen, K. Hollar, N. Breil, X. Li, M. Jin, C. Lazik, J. Lee, H. Maynard, N. Variam, A. Mayur, S. Kim, H. Chung, M. Chudzik, R. Hung, N. Yoshida, N. Kim","doi":"10.1109/VLSIT.2016.7573383","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573383","url":null,"abstract":"We report a record-setting low NMOS contact resistivity of 1.2×10<sup>-9</sup> Ωcm<sup>2</sup> compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as post implant anneal provides a promising pathway to further improve NMOS ρ<sub>C</sub> to below 1×10<sup>-9</sup> Ωcm<sup>2</sup> for the post 7 nm nodes.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128101091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
A multiple-string hybrid LED driver with 97% power efficiency and 0.996 power factor 具有97%的功率效率和0.996的功率因数的多串混合LED驱动器
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573396
Lisong Li, Yuan Gao, P. Mok
{"title":"A multiple-string hybrid LED driver with 97% power efficiency and 0.996 power factor","authors":"Lisong Li, Yuan Gao, P. Mok","doi":"10.1109/VLSIT.2016.7573396","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573396","url":null,"abstract":"This paper presents a multiple-string hybrid LED driver powered by 100-120VAC input for general lighting applications. The proposed hybrid LED driver adaptively switches between Linear Mode and Switching Mode according to the input voltage to enhance the power efficiency. This work achieves 97% power efficiency and 0.996 power factor at 120VAC 60Hz input.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132522566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
White spots reduction by ultimate proximity metal gettering at carbon complexes formed underneath contact area in CMOS image sensors 在CMOS图像传感器接触区域下方形成的碳配合物上，通过最终接近金属吸光来减少白斑
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573447
T. Yamaguchi, T. Yamashita, T. Kamino, Yotaro Goto, T. Kuroi, M. Matsuura
{"title":"White spots reduction by ultimate proximity metal gettering at carbon complexes formed underneath contact area in CMOS image sensors","authors":"T. Yamaguchi, T. Yamashita, T. Kamino, Yotaro Goto, T. Kuroi, M. Matsuura","doi":"10.1109/VLSIT.2016.7573447","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573447","url":null,"abstract":"White spots reduction by the ultimate proximity metal-gettering technology for CMOS image sensors is demonstrated. Metal contaminants in photodiodes (PDs) causing white spots can be captured by carbon complexes, as metal gettering sites, formed underneath contact areas in CMOS image sensors without any layout area penalty. High density carbon complexes take advantage of the ultimate proximity to PDs to trap not only Fe and Ni as fast diffusion metal but also W as slow diffusion metal. The optimization of the gettering site layout resulted in neither the increase of mean dark current nor the degradation of transistor performances in the pixel area. Furthermore, the optimization of the C implantation and post treatment (PT) effectively reduced white spots by about one order. This ultimate proximity metal gettering is a promising technology for high image-quality CMOS image-sensors.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121470900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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