Shien-Yang Wu, C. Y. Lin, M. Chiang, J. Liaw, J. Cheng, C. H. Chang, V. Chang, K. Pan, C. Tsai, C. Yao, T. Miyashita, Y. Wu, K. Ting, C. Hsieh, R. F. Tsui, R. Chen, C. Yang, H. Chang, C. Lee, K. Chen, Y. Ku, S. Jang
{"title":"Demonstration of a sub-0.03 um2 high density 6-T SRAM with scaled bulk FinFETs for mobile SOC applications beyond 10nm node","authors":"Shien-Yang Wu, C. Y. Lin, M. Chiang, J. Liaw, J. Cheng, C. H. Chang, V. Chang, K. Pan, C. Tsai, C. Yao, T. Miyashita, Y. Wu, K. Ting, C. Hsieh, R. F. Tsui, R. Chen, C. Yang, H. Chang, C. Lee, K. Chen, Y. Ku, S. Jang","doi":"10.1109/VLSIT.2016.7573390","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573390","url":null,"abstract":"For the first time, we demonstrate the smallest, fully functional 32Mb 6-T high density SRAM reported in literature with scaled bulk FinFETs for CMOS technology beyond 10nm node. Scaled FinFET devices exhibit excellent electrostatic with DIBL of <;45mV/V and sub-threshold swing of <;65mV/decade and competitive drive current. Static noise margin of ~90mV for the high density SRAM operated down to 0.45V is achieved.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124599250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Mitard, L. Witters, Y. Sasaki, H. Arimura, A. Schulze, R. Loo, L. Ragnarsson, A. Hikavyy, D. Cott, T. Chiarella, S. Kubicek, H. Mertens, R. Ritzenthaler, C. Vrancken, P. Favia, H. Bender, N. Horiguchi, K. Barla, D. Mocuta, A. Mocuta, N. Collaert, A. Thean
{"title":"A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs","authors":"J. Mitard, L. Witters, Y. Sasaki, H. Arimura, A. Schulze, R. Loo, L. Ragnarsson, A. Hikavyy, D. Cott, T. Chiarella, S. Kubicek, H. Mertens, R. Ritzenthaler, C. Vrancken, P. Favia, H. Bender, N. Horiguchi, K. Barla, D. Mocuta, A. Mocuta, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2016.7573368","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573368","url":null,"abstract":"Sub-30nm LG Fin-replacement strained-Germanium pFinFETs at state-of-art device dimensions are reported with optimized S/D junctions and RMG stack. Competitive performance is shown for the first time when comparing the sGe devices with counterparts from the same 14-16nm R&D platform (Ge vs Si channel, FinFET vs lateral Gate All around). Improvement in channel passivation efficiency at scaled device features is seen to be an important knob to further boost the performance of scaled Ge channel FINFETs.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114836705","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Chiu, Chun‐Hu Cheng, Chun-Yen Chang, Ying-Tsan Tang, Min-Cheng Chen
{"title":"One-transistor ferroelectric versatile memory: Strained-gate engineering for realizing energy-efficient switching and fast negative-capacitance operation","authors":"Y. Chiu, Chun‐Hu Cheng, Chun-Yen Chang, Ying-Tsan Tang, Min-Cheng Chen","doi":"10.1109/VLSIT.2016.7573414","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573414","url":null,"abstract":"In this work, we report a ferroelectric versatile memory (FE-VM) with strained-gate engineering. The memory window of high strain case was improved by ~47% at the same ferroelectric thickness, which agrees with the increase of orthorhombic crystallinity. Based on a reliable first principle calculation (FPC), we clarify that the gate strain accelerates the phase transformation from metastable monoclinic to orthorhombic and thus largely enhances the ferroelectric polarization without increasing dielectric thickness. On the other hand, the orthorhombic FE-AFE phase transition plays a key role in realizing negative capacitance (NC) effect at high gate electric field. This 1T strained-gate FE-VM with ferroelectric NC achieves a sub-60-mVdec subthreshold swing (SS) over ~4 decade of ID to provide a 1~10 fA/μm Ioff and >108 Ion/Ioff ratio, which allows for a fast 20-ns P/E switching during 1012 cycling endurance.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121620700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Fujii, Y. Kamimuta, T. Ino, Y. Nakasaki, R. Takaishi, M. Saitoh
{"title":"First demonstration and performance improvement of ferroelectric HfO2-based resistive switch with low operation current and intrinsic diode property","authors":"S. Fujii, Y. Kamimuta, T. Ino, Y. Nakasaki, R. Takaishi, M. Saitoh","doi":"10.1109/VLSIT.2016.7573413","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573413","url":null,"abstract":"We demonstrate, for the first time, a CMOS compatible ferroelectric HfO2-based two-terminal non-volatile resistive switch; HfO2 ferroelectric tunnel junction (FTJ). The device has characteristics of nA-range operation current, self-compliance, and intrinsic diode properties, as well as good device to device uniformity. Simultaneous achievement of these characteristics, which was not reported in the other two-terminal emerging memories, is significant advantage for future non-volatile applications. Accurate understanding of switching mechanism based on first-principles calculations and material characterization enabled us to establish a solid guideline for performance improvement: scaling of both ferroelectric layer and interfacial layer thickness. As a consequence, reduction of operation voltage while maintaining sufficient ON/OFF ratio was successfully demonstrated.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115517929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Saida, S. Kashiwada, Megumi Yakabe, T. Daibou, Naoki Hase, M. Fukumoto, S. Miwa, Yoshishige Suzuki, H. Noguchi, S. Fujita, J. Ito
{"title":"Sub-3 ns pulse with sub-100 µA switching of 1x–2x nm perpendicular MTJ for high-performance embedded STT-MRAM towards sub-20 nm CMOS","authors":"D. Saida, S. Kashiwada, Megumi Yakabe, T. Daibou, Naoki Hase, M. Fukumoto, S. Miwa, Yoshishige Suzuki, H. Noguchi, S. Fujita, J. Ito","doi":"10.1109/VLSIT.2016.7573412","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573412","url":null,"abstract":"A novel perpendicular magnetic tunnel junction (MTJ) is developed that can be switched using pulse widths of around 1 ns and currents of less than 100 μA. This paper presents the first demonstration in novel achievement of fast switching, low power operation and size scalability of write current down to 16 nm diameter MTJ. This MTJ satisfies retention which is typically required in cache memory. Measurement results show that our proposed MTJ can open a path to embedded STT-MRAM in sub-20 nm CMOS generation.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124961522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Czornomaz, V. Djara, V. Deshpande, E. O'Connor, M. Sousa, D. Caimi, K. Cheng, J. Fompeyrine
{"title":"First demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si using selective epitaxy and standard FEOL processes","authors":"L. Czornomaz, V. Djara, V. Deshpande, E. O'Connor, M. Sousa, D. Caimi, K. Cheng, J. Fompeyrine","doi":"10.1109/VLSIT.2016.7573391","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573391","url":null,"abstract":"We report the first demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si, fabricated with InGaAs selective epitaxy and standard front end of line (FEOL) processes. This novel and scalable CMOS integration scheme enables InGaAs nFET fabrication in close proximity to SiGe pFETs (down to 25 nm spacing), resulting in 6T-SRAM arrays having a minimum cell size below 0.45 μm2. This scheme can be combined with any bulk Si or SOI-based planar or fin technology, and is compatible with standard large-area Si substrate. Individual InGaAs nFETs and SiGe pFETs are fabricated with a standard self-aligned CMOS-compatible process flow and feature LG scaled down to 35 nm. Moreover, the InGaAs nFET process flow includes selective epitaxy, raised source/drain (RSD) and high-k/metal gate (HKMG) modules. Finally, we report electrical characterization of isolated FETs and inverters as well as dense SRAM cells with planar and fin- FETs.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134147018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Vais, A. Alian, L. Nyns, J. Franco, S. Sioncke, V. Putcha, H. Yu, Y. Mols, R. Rooyackers, D. Lin, J. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, A. Mocuta, N. Collaert, K. De Meyer, A. Thean
{"title":"Record mobility (μeff ∼3100 cm2/V-s) and reliability performance (Vov∼0.5V for 10yr operation) of In0.53Ga0.47As MOS devices using improved surface preparation and a novel interfacial layer","authors":"A. Vais, A. Alian, L. Nyns, J. Franco, S. Sioncke, V. Putcha, H. Yu, Y. Mols, R. Rooyackers, D. Lin, J. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, A. Mocuta, N. Collaert, K. De Meyer, A. Thean","doi":"10.1109/VLSIT.2016.7573410","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573410","url":null,"abstract":"In<sub>0.53</sub>Ga<sub>0.47</sub>As quantum-well (QW) MOSFETs with a novel interfacial layer(IL)/high-k stack on an improved interface were fabricated. Excellent device characteristics (SS~72mV/dec, I<sub>on</sub>/I<sub>off</sub>>10<sup>6</sup> at V<sub>ds</sub>=0.5V, DIBL~26mV/v for a device at EOT~1.25nm) were obtained. In addition, EOT was scaled down to 1.0 nm without a significant degradation in electrical properties. The extracted field-effect mobility (peak μ<sub>eff</sub> ~3100 cm<sup>2</sup>/V-s for EOT~1.25nm and μ<sub>eff</sub> ~ 2400 cm<sup>2</sup>/V-s for EOT~1.0nm) is the highest split C-V mobility reported for surface channel In<sub>0.53</sub>Ga<sub>0.47</sub>As MOSFETs at such small EOT. We demonstrate a record reliability performance using the new IL with an overdrive voltage, V<sub>ov</sub>~0.5V for a 10 year operation (with maximum ΔV<sub>th</sub>=30mV) at EOT~1.25nm. We attribute this performance enhancement in mobility to reduced surface roughness (extremely smooth surface) and remote phonon scattering (due to IL), and improvement in reliability to enhanced energy misalignment between defect bands in high-k and charge carriers in the semi-conductor respectively.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134459787","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Meng-Chun Shih, Chia-Yu Wang, Yung-Huei Lee, Wayne Wang, L. Thomas, Huanlong Liu, Jian Zhu, Yuan-Jen Lee, G. Jan, Yu-Jen Wang, T. Zhong, T. Torng, P. Wang, D. Lin, T. Chiang, K. Shen, H. Chuang, W. Gallagher
{"title":"Reliability study of perpendicular STT-MRAM as emerging embedded memory qualified for reflow soldering at 260°C","authors":"Meng-Chun Shih, Chia-Yu Wang, Yung-Huei Lee, Wayne Wang, L. Thomas, Huanlong Liu, Jian Zhu, Yuan-Jen Lee, G. Jan, Yu-Jen Wang, T. Zhong, T. Torng, P. Wang, D. Lin, T. Chiang, K. Shen, H. Chuang, W. Gallagher","doi":"10.1109/VLSIT.2016.7573411","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573411","url":null,"abstract":"A comprehensive reliability analysis of perpendicular Spin-Transfer-Torque Magnetic Random Access Memory (pSTT-MRAM) is demonstrated that pSTT-MRAM is capable of fast write, more than 107 cycles endurance, less than 10-20 read disturb error rate at 125°C, and 10 years data retention up to 225°C at chip level. Furthermore, we prove for the first time that pSTT-MRAM technology can withstand reflow soldering at 260°C, thus enabling the opportunity for embedded nonvolatile memories in consumer and automotive Microcontrollers (MCUs) applications.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"337 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134475367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Cutaia, K. Moselund, H. Schmid, M. Borg, A. Olziersky, H. Riel
{"title":"Complementary III–V heterojunction lateral NW Tunnel FET technology on Si","authors":"D. Cutaia, K. Moselund, H. Schmid, M. Borg, A. Olziersky, H. Riel","doi":"10.1109/VLSIT.2016.7573444","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573444","url":null,"abstract":"We demonstrate for the first time a technology which allows the monolithic integration of both p-type (InAs-Si) and n-type (InAs-GaSb) heterojunction Tunnel FETs (TFET) laterally on a Si substrate. The lateral heterojunction nanowire (NW) structures are implemented using top-down CMOS-compatible processes combined with Template-Assisted Selective Epitaxy (TASE) [1] of the III-V materials. Sub-40nm InAs-Si p-TFETs and InAs-GaSb n-TFETs have been fabricated and represent to the best of our knowledge the first lateral III-V heterostructure NW TFETs. The InAs-Si p-TFETs show excellent performance with average subthreshold swing, SSave, of ~70mV/dec. combined with an on-current, Ion, of 4μA/μm at VDS = VGS = -0.5V. The InAs-GaSb n-TFETs have about an order of magnitude higher Ion, but SS is deteriorated due to high interface traps density (Dit).","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122538896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Yoshimoto, Y. Katoh, S. Ogasahara, Z. Wei, K. Kouno
{"title":"A ReRAM-based physically unclonable function with bit error rate < 0.5% after 10 years at 125°C for 40nm embedded application","authors":"Y. Yoshimoto, Y. Katoh, S. Ogasahara, Z. Wei, K. Kouno","doi":"10.1109/VLSIT.2016.7573433","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573433","url":null,"abstract":"This paper presents a secure application-a physically unclonable function (PUF)-that uses the physical property of resistive random access memory (ReRAM). The proposed PUF-generating method and reproducing algorithm achieves highly reliable with bit error rate (BER) <; 0.5% and reproduction exceeding 1010 times at -40 to 125°C after 10 years at 125°C and high uniqueness as evidenced by passing NIST tests. Evaluations on 40nm ReRAM test chips have demonstrated the feasibility of a scaled-down ReRAM cell enhanced with PUF.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122793850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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