J. Mitard, L. Witters, Y. Sasaki, H. Arimura, A. Schulze, R. Loo, L. Ragnarsson, A. Hikavyy, D. Cott, T. Chiarella, S. Kubicek, H. Mertens, R. Ritzenthaler, C. Vrancken, P. Favia, H. Bender, N. Horiguchi, K. Barla, D. Mocuta, A. Mocuta, N. Collaert, A. Thean
{"title":"第二代14/16nm节点兼容应变ge pFINFET,性能优于先进的si沟道finfet","authors":"J. Mitard, L. Witters, Y. Sasaki, H. Arimura, A. Schulze, R. Loo, L. Ragnarsson, A. Hikavyy, D. Cott, T. Chiarella, S. Kubicek, H. Mertens, R. Ritzenthaler, C. Vrancken, P. Favia, H. Bender, N. Horiguchi, K. Barla, D. Mocuta, A. Mocuta, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2016.7573368","DOIUrl":null,"url":null,"abstract":"Sub-30nm LG Fin-replacement strained-Germanium pFinFETs at state-of-art device dimensions are reported with optimized S/D junctions and RMG stack. Competitive performance is shown for the first time when comparing the sGe devices with counterparts from the same 14-16nm R&D platform (Ge vs Si channel, FinFET vs lateral Gate All around). Improvement in channel passivation efficiency at scaled device features is seen to be an important knob to further boost the performance of scaled Ge channel FINFETs.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs\",\"authors\":\"J. Mitard, L. Witters, Y. Sasaki, H. Arimura, A. Schulze, R. Loo, L. Ragnarsson, A. Hikavyy, D. Cott, T. Chiarella, S. Kubicek, H. Mertens, R. Ritzenthaler, C. Vrancken, P. Favia, H. Bender, N. Horiguchi, K. Barla, D. Mocuta, A. Mocuta, N. Collaert, A. Thean\",\"doi\":\"10.1109/VLSIT.2016.7573368\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Sub-30nm LG Fin-replacement strained-Germanium pFinFETs at state-of-art device dimensions are reported with optimized S/D junctions and RMG stack. Competitive performance is shown for the first time when comparing the sGe devices with counterparts from the same 14-16nm R&D platform (Ge vs Si channel, FinFET vs lateral Gate All around). Improvement in channel passivation efficiency at scaled device features is seen to be an important knob to further boost the performance of scaled Ge channel FINFETs.\",\"PeriodicalId\":129300,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Technology\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2016.7573368\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573368","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 2nd Generation of 14/16nm-node compatible strained-Ge pFINFET with improved performance with respect to advanced Si-channel FinFETs
Sub-30nm LG Fin-replacement strained-Germanium pFinFETs at state-of-art device dimensions are reported with optimized S/D junctions and RMG stack. Competitive performance is shown for the first time when comparing the sGe devices with counterparts from the same 14-16nm R&D platform (Ge vs Si channel, FinFET vs lateral Gate All around). Improvement in channel passivation efficiency at scaled device features is seen to be an important knob to further boost the performance of scaled Ge channel FINFETs.