采用选择性外延和标准FEOL工艺首次展示了InGaAs/SiGe CMOS逆变器和Si上的密集SRAM阵列

L. Czornomaz, V. Djara, V. Deshpande, E. O'Connor, M. Sousa, D. Caimi, K. Cheng, J. Fompeyrine
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引用次数: 13

摘要

我们报道了采用InGaAs选择性外延和标准前端线(FEOL)工艺制造的InGaAs/SiGe CMOS逆变器和Si上密集SRAM阵列的首次演示。这种新颖且可扩展的CMOS集成方案使InGaAs nFET的制造与SiGe pfet非常接近(最小间距为25 nm),从而使6T-SRAM阵列的最小单元尺寸低于0.45 μm2。该方案可与任何块体硅或基于soi的平面或翅片技术相结合,并与标准大面积硅衬底兼容。单个InGaAs nfet和SiGe pfet采用标准的自对准cmos兼容工艺流程制造,并具有LG缩小到35 nm的功能。此外,InGaAs nFET工艺流程包括选择性外延,提高源/漏极(RSD)和高k/金属栅极(HKMG)模块。最后,我们报告了隔离场效应管和逆变器的电特性,以及具有平面和鳍状场效应管的密集SRAM电池。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
First demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si using selective epitaxy and standard FEOL processes
We report the first demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si, fabricated with InGaAs selective epitaxy and standard front end of line (FEOL) processes. This novel and scalable CMOS integration scheme enables InGaAs nFET fabrication in close proximity to SiGe pFETs (down to 25 nm spacing), resulting in 6T-SRAM arrays having a minimum cell size below 0.45 μm2. This scheme can be combined with any bulk Si or SOI-based planar or fin technology, and is compatible with standard large-area Si substrate. Individual InGaAs nFETs and SiGe pFETs are fabricated with a standard self-aligned CMOS-compatible process flow and feature LG scaled down to 35 nm. Moreover, the InGaAs nFET process flow includes selective epitaxy, raised source/drain (RSD) and high-k/metal gate (HKMG) modules. Finally, we report electrical characterization of isolated FETs and inverters as well as dense SRAM cells with planar and fin- FETs.
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