Record mobility (μeff ∼3100 cm2/V-s) and reliability performance (Vov∼0.5V for 10yr operation) of In0.53Ga0.47As MOS devices using improved surface preparation and a novel interfacial layer

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI:10.1109/VLSIT.2016.7573410

A. Vais, A. Alian, L. Nyns, J. Franco, S. Sioncke, V. Putcha, H. Yu, Y. Mols, R. Rooyackers, D. Lin, J. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, A. Mocuta, N. Collaert, K. De Meyer, A. Thean

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引用次数: 10

Abstract

In_0.53Ga_0.47As quantum-well (QW) MOSFETs with a novel interfacial layer(IL)/high-k stack on an improved interface were fabricated. Excellent device characteristics (SS~72mV/dec, I_on/I_off>10⁶ at V_ds=0.5V, DIBL~26mV/v for a device at EOT~1.25nm) were obtained. In addition, EOT was scaled down to 1.0 nm without a significant degradation in electrical properties. The extracted field-effect mobility (peak μ_eff ~3100 cm²/V-s for EOT~1.25nm and μ_eff ~ 2400 cm²/V-s for EOT~1.0nm) is the highest split C-V mobility reported for surface channel In_0.53Ga_0.47As MOSFETs at such small EOT. We demonstrate a record reliability performance using the new IL with an overdrive voltage, V_ov~0.5V for a 10 year operation (with maximum ΔV_th=30mV) at EOT~1.25nm. We attribute this performance enhancement in mobility to reduced surface roughness (extremely smooth surface) and remote phonon scattering (due to IL), and improvement in reliability to enhanced energy misalignment between defect bands in high-k and charge carriers in the semi-conductor respectively.

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使用改进的表面制备和新的界面层，记录了In0.53Ga0.47As MOS器件的迁移率(μeff ~ 3100 cm2/V-s)和可靠性性能(Vov ~ 0.5V, 10年运行)

在改进的界面上制备了具有新型界面层(IL)/高k堆叠的In0.53Ga0.47As量子阱(QW) mosfet。获得了优良的器件特性(在Vds=0.5V时SS~72mV/dec, Ion/Ioff>106, EOT~1.25nm时DIBL~26mV/v)。此外，EOT被缩小到1.0 nm，而电性能没有明显下降。所提取的场效应迁移率(EOT~1.25nm时的峰值μeff ~3100 cm2/V-s, EOT~1.0nm时的峰值μeff ~ 2400 cm2/V-s)是在如此小的EOT下报道的表面沟道In0.53Ga0.47As mosfet中最高的分裂C-V迁移率。在EOT~1.25nm下，我们使用具有超速电压(Vov~0.5V)的新IL，在10年的工作中(最大ΔVth=30mV)展示了创纪录的可靠性性能。我们将这种迁移率的性能增强归因于表面粗糙度(极其光滑的表面)和远程声子散射(由于IL)的降低，以及可靠性的提高分别归因于高k载流子和半导体中载流子缺陷带之间能量错位的增强。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 IEEE Symposium on VLSI Technology

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