S. Fukami, T. Anekawa, Ayato Ohkawara, Chaoliang Zhang, H. Ohno
{"title":"A sub-ns three-terminal spin-orbit torque induced switching device","authors":"S. Fukami, T. Anekawa, Ayato Ohkawara, Chaoliang Zhang, H. Ohno","doi":"10.1109/VLSIT.2016.7573379","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573379","url":null,"abstract":"We show a three-terminal spintronics memory device, which can be reliably switched by 0.5-ns current pulses with small magnitude. A new device geometry is employed, where spin-orbit torque is used for the write operation. We also show that an improved structure realizes magnetic field-free switching and employing a material other than the standard Ta can lead to a reduction of the switching current by more than half.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123728695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Brunet, P. Batude, C. Fenouillet-Béranger, P. Besombes, L. Hortemel, F. Ponthenier, B. Previtali, C. Tabone, A. Royer, C. Agraffeil, C. Euvrard-Colnat, A. Seignard, C. Morales, F. Fournel, L. Benaissa, T. Signamarcheix, P. Besson, M. Jourdan, R. Kachtouli, V. Benevent, J. Hartmann, C. Comboroure, N. Allouti, N. Possémé, C. Vizioz, C. Arvet, S. Barnola, S. Kerdilès, L. Baud, L. Pasini, C-M. V. Lu, F. Deprat, A. Toffoli, G. Romano, C. Guedj, V. Delaye, F. Boeuf, O. Faynot, M. Vinet
{"title":"First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers","authors":"L. Brunet, P. Batude, C. Fenouillet-Béranger, P. Besombes, L. Hortemel, F. Ponthenier, B. Previtali, C. Tabone, A. Royer, C. Agraffeil, C. Euvrard-Colnat, A. Seignard, C. Morales, F. Fournel, L. Benaissa, T. Signamarcheix, P. Besson, M. Jourdan, R. Kachtouli, V. Benevent, J. Hartmann, C. Comboroure, N. Allouti, N. Possémé, C. Vizioz, C. Arvet, S. Barnola, S. Kerdilès, L. Baud, L. Pasini, C-M. V. Lu, F. Deprat, A. Toffoli, G. Romano, C. Guedj, V. Delaye, F. Boeuf, O. Faynot, M. Vinet","doi":"10.1109/VLSIT.2016.7573428","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573428","url":null,"abstract":"For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130138514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Ramesh, T. Ivanov, E. Camerotto, N. Sun, J. Franco, A. Sibaja-Hernandez, R. Rooyackers, A. Alian, J. Loo, A. Veloso, A. Milenin, D. Lin, P. Favia, H. Bender, N. Collaert, A. Thean, K. De Meyer
{"title":"Top-down InGaAs nanowire and fin vertical FETs with record performance","authors":"S. Ramesh, T. Ivanov, E. Camerotto, N. Sun, J. Franco, A. Sibaja-Hernandez, R. Rooyackers, A. Alian, J. Loo, A. Veloso, A. Milenin, D. Lin, P. Favia, H. Bender, N. Collaert, A. Thean, K. De Meyer","doi":"10.1109/VLSIT.2016.7573419","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573419","url":null,"abstract":"Vertical nanowires and for the first time vertical fins, dry etched from the same lattice matched InGaAs on InP, are used to fabricate MOSFETs. Single and multiple pillar array devices exhibit excellent electrostatics with min SS = 68mV/dec (VDS=0.05V) and max Gm = 580μS/μm (VDS=0.4V). These are the first III-V pillar array devices fabricated with top-down approach. Linear Ion scaling with effective width and overall Vth uniformity makes this result the first step in assessing the manufacturability of this integration scheme. A reliability analysis puts these vertical MOSFETs in line with other IIIV devices with similar gate stack, indicating that the IIIV etch does not introduce additional interface defects.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128393595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Y. Wang, B. Cheng, X. Wang, E. Towie, C. Riddet, A. Brown, S. Amoroso, L. Wang, D. Reid, X. Liu, J. Kang, A. Asenov
{"title":"Variability-aware TCAD based design-technology co-optimization platform for 7nm node nanowire and beyond","authors":"Y. Wang, B. Cheng, X. Wang, E. Towie, C. Riddet, A. Brown, S. Amoroso, L. Wang, D. Reid, X. Liu, J. Kang, A. Asenov","doi":"10.1109/VLSIT.2016.7573423","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573423","url":null,"abstract":"In this work, a design-technology co-optimization (DTCO) platform for 7nm node nanowire and beyond is demonstrated for the first time. The platform extends from predictive TCAD simulations through compact model extraction to circuit simulation. The impact of different cross-section geometries, design of experiment, parasitic effects, global variation and local variation are accurately and efficiently examined to provide insights for variability-aware device/circuit co-optimization.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122823676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dechao Guo, G. Karve, Gen Tsutsui, K. Lim, R. Robison, T. Hook, Reinaldo A. Vega, Derrick Liu, S. Bedell, S. Mochizuki, F. Lie, Kerem Akarvardar, Miaomiao Wang, Ruqiang Bao, Sean D. Burns, Victor Chan, K. Cheng, J. Demarest, Jody A. Fronheiser, Pouya Hashemi, James J. Kelly, Jinghong Li, Nicolas Loubet, P. Montanini, Bhagawan Sahu, M. Sankarapandian, S. Sieg, J. Sporre, J. Strane, R. Southwick, N. Tripathi, R. Venigalla, Junli Wang, Koji Watanabe, C. Yeung, D. Gupta, Bruce B. Doris, Nelson Felix, Ajey Poovannummoottil Jacob, H. Jagannathan, S. Kanakasabapathy, Renee T. Mo, Vijay Narayanan, D. Sadana, P. Oldiges, J. Stathis, T. Yamashita, V. Paruchuri, M. Colburn, Andreas Knorr, R. Divakaruni, H. Bu, M. Khare
{"title":"FINFET technology featuring high mobility SiGe channel for 10nm and beyond","authors":"Dechao Guo, G. Karve, Gen Tsutsui, K. Lim, R. Robison, T. Hook, Reinaldo A. Vega, Derrick Liu, S. Bedell, S. Mochizuki, F. Lie, Kerem Akarvardar, Miaomiao Wang, Ruqiang Bao, Sean D. Burns, Victor Chan, K. Cheng, J. Demarest, Jody A. Fronheiser, Pouya Hashemi, James J. Kelly, Jinghong Li, Nicolas Loubet, P. Montanini, Bhagawan Sahu, M. Sankarapandian, S. Sieg, J. Sporre, J. Strane, R. Southwick, N. Tripathi, R. Venigalla, Junli Wang, Koji Watanabe, C. Yeung, D. Gupta, Bruce B. Doris, Nelson Felix, Ajey Poovannummoottil Jacob, H. Jagannathan, S. Kanakasabapathy, Renee T. Mo, Vijay Narayanan, D. Sadana, P. Oldiges, J. Stathis, T. Yamashita, V. Paruchuri, M. Colburn, Andreas Knorr, R. Divakaruni, H. Bu, M. Khare","doi":"10.1109/VLSIT.2016.7573360","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573360","url":null,"abstract":"SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1-4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1-4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122365993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Back-illuminated voltage-domain global shutter CMOS image sensor with 3.75µm pixels and dual in-pixel storage nodes","authors":"L. Stark, J. Raynor, F. Lalanne, R. Henderson","doi":"10.1109/VLSIT.2016.7573451","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573451","url":null,"abstract":"A 1024×800 image sensor with voltage-domain global shutter pixels and dual in-pixel storage is implemented in a 90nm/65nm back-illuminated (BSI) imaging process. The pixel has a 3.75μm pitch, achieves -80dB PLS operating in its correlated double sampling mode and has a maximum dynamic range in its high-dynamic range imaging mode of 102dB.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132868005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Hsieh, Y. D. Wang, S. Chung, J. Ke, C. Yang, S. Hsu
{"title":"A new variation plot to examine the interfacial-dipole induced work-function variation in advanced high-k metal-gate CMOS devices","authors":"E. Hsieh, Y. D. Wang, S. Chung, J. Ke, C. Yang, S. Hsu","doi":"10.1109/VLSIT.2016.7573435","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573435","url":null,"abstract":"The interfacial dipole and bulk trap in HKMG stack have been found to be significant to the work function variation (σVWF), in addition to the metal grains. In order to differentiate their effects on σVWF, a new variation plot is proposed and the dipole and trap effects can be distinguished. Here, we propose a simple experimental method to separate the effects of MG/HK and HK/IL interfacial dipoles. In pMOSFET, HK/IL dipoles dominate HK induced variation; MG/HK dipoles are dominant in nMOSFET. However, in terms of the reliability test, after PBTI stress, HK bulk traps play a major role in the variation of nMOSFET, while after NBTI, HK/IL dipoles are strengthened by hydrogen bonds and still dominant in work function variation of pMOSFET. Design guideline is provided to deal with the passivation of high-k traps by nitrogen concentration and the improvement of variability in HKMG CMOS devices.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"12 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131726391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Nii, M. Yabuuchi, Y. Ishii, Miki Tanaka, M. Igarashi, K. Fukuoka, S. Tanaka
{"title":"A dynamic/static SRAM power management scheme for DVFS and AVS in advanced automotive infotainment SoCs","authors":"K. Nii, M. Yabuuchi, Y. Ishii, Miki Tanaka, M. Igarashi, K. Fukuoka, S. Tanaka","doi":"10.1109/VLSIT.2016.7573395","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573395","url":null,"abstract":"An embedded SRAM power management scheme using 16 nm FinFET technology is demonstrated in automotive infotainment SoCs. By introducing write-assist circuit technique, SRAM can operate down to 0.5 V wide voltage range, achieving DVFS for efficient power saving. Fast resume standby mode is also developed for reducing the leakage power of L1 cache under 2 GHz CPU operation. We confirmed that proposed thermal control scheme can be protected by thermal runaway failure.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131873218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Broadband THz spectroscopic imaging based on a fully-integrated 4×2 Digital-to-Impulse radiating array with a full-spectrum of 0.03–1.03THz in silicon","authors":"M. Assefzadeh, A. Babakhani","doi":"10.1109/VLSIT.2016.7573401","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573401","url":null,"abstract":"This paper presents a broadband THz frequency-comb spectroscopic imager based on a fully-integrated 4×2 picosecond Direct Digital-to-Impulse (D2I) radiating array. By employing a novel trigger-based beamforming architecture, the chip performs coherent spatial combining of broadband radiated pulses and achieves an SNR>1 BW of 1.03THz (at the receiver) with a pulse peak EIRP of 30dBm. Time-domain radiation is characterized using a fsec-laser-based THz sampler and a pulse width of 5.4ps is measured. Spectroscopic imaging of metal, plastic, and cellulose capsules (empty and filled) are demonstrated. This chip achieves signal generation with an available full-spectrum of 0.03-1.03THz. The 8-element single-chip array is fabricated in a 90nm SiGe BiCMOS process.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133696686","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Study of wake-up and fatigue properties in doped and undoped ferroelectric HfO2 in conjunction with piezo-response force microscopy analysis","authors":"S. Shibayama, L. Xu, S. Migita, A. Toriumi","doi":"10.1109/VLSIT.2016.7573415","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573415","url":null,"abstract":"This paper reports wake-up and fatigue effects in ferroelectric HfO2 with and without Y-doping by comparing macroscopic capacitor characteristics with nano-level piezo-response force microscopy (PFM) analysis. Even though initial characteristics are almost the same between with and without Y-doping, endurance characteristics are really different macroscopically, and PFM study microscopically supports the endurance characteristics as well. This fact suggests that the robustness of HfO2 ferroelectricity should be sensitive to the doping.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121412839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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