2016 IEEE Symposium on VLSI Technology最新文献_第4页

Deep insight into process-induced pre-existing traps and PBTI stress-induced trap generations in high-k gate dielectrics through systematic RTN characterizations and ab initio calculations 通过系统的RTN表征和从头计算，深入了解高k栅极介质中工艺诱导的预先存在陷阱和PBTI应力诱导的陷阱

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573373

Jiezhi Chen, Y. Nakasaki, Y. Mitani

引用次数: 2

Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm 在300mm Si平台上集成InGaAs栅极全能场效应管的可扩展性:通道宽度降至7nm, Lg降至36nm的演示

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573420

X. Zhou, N. Waldron, G. Boccardi, F. Sebaai, C. Merckling, G. Eneman, S. Sioncke, L. Nyns, A. Opdebeeck, J. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, W. Guo, B. Kunert, L. Teugels, K. Devriendt, A. S. Hernandez, J. Franco, D. V. van Dorp, K. Barla, N. Collaert, A. Thean

引用次数: 18

The age of sensors - How MEMS sensors will enable the next wave of new products. 传感器的时代- MEMS传感器将如何使下一波新产品成为可能。

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573357

S. Lloyd, M. Lim

引用次数: 6

Ultralow-resistivity CMOS contact scheme with pre-contact amorphization plus Ti (germano-)silicidation 超低电阻率CMOS接触方案与预接触非晶化加钛(锗)硅化

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573381

H. Yu, M. Schaekers, A. Hikavyy, E. Rosseel, A. Peter, K. Hollar, F. Khaja, W. Aderhold, L. Date, A. Mayur, J. lee, K. Shin, B. Douhard, S. Chew, S. Demuynck, S. Kubicek, D. Kim, A. Mocuta, K. Barla, N. Horiguchi, N. Collaert, A. Thean, K. De Meyer

引用次数: 29

High-density user-programmable logic array based on adjacent integration of pure-CMOS crossbar antifuse into logic CMOS circuits 高密度用户可编程逻辑阵列，基于相邻集成的纯CMOS交叉防熔丝到逻辑CMOS电路

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573364

S. Yasuda, Masato Oda, M. Matsumoto, K. Tatsumura, K. Zaitsu, Y. Ho, M. Ono

引用次数: 1

Demonstration of record SiGe transconductance and short-channel current drive in High-Ge-Content SiGe PMOS FinFETs with improved junction and scaled EOT 具有改进结和缩放EOT的高锗含量SiGe PMOS finfet中创纪录的SiGe跨导和短通道电流驱动的演示

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573370

P. Hashemi, K. Lee, T. Ando, K. Balakrishnan, J. Ott, S. Koswatta, S. Engelmann, Dae-gyu Park, V. Narayanan, R. Mo, E. Leobandung

引用次数: 7

Intelligent mobility realized through VLSI 通过VLSI实现智能移动

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573358

T. Asami

引用次数: 0

InGaAs nanowire MOSFETs with ION = 555 µA/µm at IOFF = 100 nA/µm and VDD = 0.5 V InGaAs纳米线mosfet, IOFF = 100 nA/µm, VDD = 0.5 V, ION = 555µA/µm

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573418

C. Zota, Fredrik Lindelow, L. Wernersson, E. Lind

引用次数: 10

Advanced non-volatile embedded memory for a wide range of applications 先进的非易失性嵌入式存储器，适用于广泛的应用

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573365

S. Kimura

引用次数: 1

Achieving Sub-ns switching of STT-MRAM for future embedded LLC applications through improvement of nucleation and propagation switching mechanisms 通过改进成核和传播切换机制，实现STT-MRAM在未来嵌入式LLC应用中的Sub-ns切换

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573362

G. Jan, L. Thomas, S. Le, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, J. Iwata-Harms, Sahil J. Patel, R. Tong, S. Serrano-Guisan, D. Shen, R. He, J. Haq, J. Teng, V. Lam, R. Annapragada, Yu-Jen Wang, T. Zhong, T. Torng, P. Wang

{"title":"Achieving Sub-ns switching of STT-MRAM for future embedded LLC applications through improvement of nucleation and propagation switching mechanisms","authors":"G. Jan, L. Thomas, S. Le, Yuan-Jen Lee, Huanlong Liu, Jian Zhu, J. Iwata-Harms, Sahil J. Patel, R. Tong, S. Serrano-Guisan, D. Shen, R. He, J. Haq, J. Teng, V. Lam, R. Annapragada, Yu-Jen Wang, T. Zhong, T. Torng, P. Wang","doi":"10.1109/VLSIT.2016.7573362","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573362","url":null,"abstract":"We present recent advances in writing speed of pSTT_MRAM which demonstrate its potential as a candidate for replacement of LCC cache for advanced technology nodes as well as applications where non-volatility may be needed. In this paper we explore the feasibility of sub-ns switching of devices and their characterization using comprehensive time resolved electrical measurement of the reversal mechanism. We show that the switching mechanism can be described as a simple nucleation followed by propagation model that can be characterized statistically. We further demonstrate that after optimization of the Magnetic Tunnel Junction (MTJ) stack, single devices can be switched reliably using write pulse length down to 750ps while preserving functionality and data retention @ 125°C. Results of the integration at array level on an 8MB test vehicle are also presented allowing full array writing using 3ns pulses without ECC and demonstrated data retention of 10 years (1ppm) at 125°C.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121996220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30