2016 IEEE Symposium on VLSI Technology最新文献

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A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs 一种高度可扩展的多晶硅无结场效应管,具有新颖的多层混合P/N层和垂直栅极,用于3D堆叠ic
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573429
Ya-Chi Cheng, Hung-Bin Chen, Chun-Yen Chang, Chun‐Hu Cheng, Yi-Jia Shih, Yung-Chun Wu
{"title":"A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs","authors":"Ya-Chi Cheng, Hung-Bin Chen, Chun-Yen Chang, Chun‐Hu Cheng, Yi-Jia Shih, Yung-Chun Wu","doi":"10.1109/VLSIT.2016.7573429","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573429","url":null,"abstract":"This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high Ion/Ioff current ratio (>109), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125467884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
GDOT: A graphene-based nanofunction for dot-product computation GDOT:基于石墨烯的点积计算纳米函数
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573377
Ning Wang, Sujan Kumar Gonugondla, Ihab Nahlus, Naresh R Shanbhag, E. Pop
{"title":"GDOT: A graphene-based nanofunction for dot-product computation","authors":"Ning Wang, Sujan Kumar Gonugondla, Ihab Nahlus, Naresh R Shanbhag, E. Pop","doi":"10.1109/VLSIT.2016.7573377","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573377","url":null,"abstract":"Though much excitement surrounds two-dimensional (2D) beyond CMOS fabrics like graphene and MoS2, most efforts have focused on individual devices, with few high-level implementations. Here we present the first graphene-based dot-product nanofunction (GDOT) using a mixed-signal architecture. Dot product kernels are essential for emerging image processing and neuromorphic computing applications, where energy efficiency is prioritized. SPICE simulations of GDOT implementing a Gaussian blur show up to ~104 greater signal-to-noise ratio (SNR) over CMOS based implementations - a direct result of higher graphene mobility in a circuit tolerant to low on/off ratios. Energy consumption is nearly equivalent, implying the GDOT can operate faster at higher SNR than CMOS counter-parts while preserving energy benefits over digital implementations. We implement a prototype 2-input GDOT on a wafer-scale 4\" process, with measured results confirming dot-product operation and lower than expected computation error.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130256380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Statistical limits of contact resistivity due to atomistic variation in nanoscale contacts 纳米级接触中原子变化引起的接触电阻率的统计限制
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573422
G. Shine, C. Weber, K. Saraswat
{"title":"Statistical limits of contact resistivity due to atomistic variation in nanoscale contacts","authors":"G. Shine, C. Weber, K. Saraswat","doi":"10.1109/VLSIT.2016.7573422","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573422","url":null,"abstract":"Using large-scale quantum transport simulations, we calculate the intrinsic variability of contact resistivity in scaled Si devices due to atomistic variation. We further demonstrate that tunneling resistance and metal band structure mismatch each account for approximately half of the increase in contact resistivity above fundamental lower bounds. The results suggest that worsening variability must be counteracted by barrier height modulation to meet targets in future technology nodes.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128005922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
RTN and low frequency noise on ultra-scaled near-ballistic Ge nanowire nMOSFETs 超尺度近弹道锗纳米线nmosfet的RTN与低频噪声
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573421
Wangran Wu, Heng Wu, M. Si, N. Conrad, Yi Zhao, P. Ye
{"title":"RTN and low frequency noise on ultra-scaled near-ballistic Ge nanowire nMOSFETs","authors":"Wangran Wu, Heng Wu, M. Si, N. Conrad, Yi Zhao, P. Ye","doi":"10.1109/VLSIT.2016.7573421","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573421","url":null,"abstract":"In this work, we present the first observation of random telegraph noise (RTN) in ultra-scaled Ge nanowire (NW) nMOSFETs. The impacts of NW geometry, channel length, EOT, and channel doping on low frequency noise are studied comprehensively. It is confirmed that the low frequency noise with 1/f characteristics is attributed to the mobility fluctuation in ultra-scaled Ge NW nMOSFETs. The low frequency noise decreases when the channel length scales down from 80 nm to 40 nm because of the near-ballistic transport of electrons.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117219519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Ultra low power coupled oscillator arrays for computer vision applications 用于计算机视觉应用的超低功耗耦合振荡器阵列
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573439
N. Shukla, Wei-Yu Tsai, M. Jerry, M. Barth, V. Narayanan, Suman Datta
{"title":"Ultra low power coupled oscillator arrays for computer vision applications","authors":"N. Shukla, Wei-Yu Tsai, M. Jerry, M. Barth, V. Narayanan, Suman Datta","doi":"10.1109/VLSIT.2016.7573439","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573439","url":null,"abstract":"Coupled oscillators provide an efficient non-Boolean paradigm for solving a variety of computationally intensive problems in computer vision. This motivates the realization of large networks of low-power coupled oscillators. In this work, we experimentally demonstrate: (i) a relaxation oscillator based on the insulator-metal transition (IMT) in vanadium dioxide (VO2) with record low DC input (peak) power of ~23 μW; (ii) a network of coupled VO2 oscillators with record number of elements (6 oscillators) which perform image processing functionalities in high dimensional space like color detection and morphological operations such as dilation and erosion). Calibrated simulations show that 10× reduction in power compared to a 32 nm CMOS accelerator at iso-throughput.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115548311","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Direct three-dimensional observation of the conduction in poly-Si and In1−xGaxAs 3D NAND vertical channels 直接三维观察多晶硅和In1−xGaxAs三维NAND垂直通道的传导
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573430
U. Celano, E. Capogreco, Judit Lisoni, A. Arreghini, Bernardette Kunert, W. Guo, G. V. D. Bosch, J. V. Houdt, K. D. Meyer, Arnaud Furnémont, Wilfried Vandervorst
{"title":"Direct three-dimensional observation of the conduction in poly-Si and In1−xGaxAs 3D NAND vertical channels","authors":"U. Celano, E. Capogreco, Judit Lisoni, A. Arreghini, Bernardette Kunert, W. Guo, G. V. D. Bosch, J. V. Houdt, K. D. Meyer, Arnaud Furnémont, Wilfried Vandervorst","doi":"10.1109/VLSIT.2016.7573430","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573430","url":null,"abstract":"Nanoscopic details of the conduction in 3D NAND vertical channels are unraveled by a novel slice-and-view tomographic technique, Scalpel SPM. The structural and electrical properties of poly-Si and single crystalline In1-xGaxAs of 45 nm channel diameters are explored/revealed. The impact of the grain boundaries (GBs) in poly-Si and of the material segregation in In1-xGaxAs are shown, thus providing a direct correlation between the channel materials and the electrical performance of the device.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127544972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Ultra low p-type SiGe contact resistance FinFETs with Ti silicide liner using cryogenic contact implantation amorphization and Solid-Phase Epitaxial Regrowth (SPER) 低温接触注入非晶化和固相外延再生(SPER)超低p型SiGe接触电阻硅化钛衬里finfet
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573384
Y. R. Yang, N. Breil, C. Y. Yang, J. Hsieh, F. Chiang, B. Colombeau, B. Guo, K. Shim, N. Variam, G. Leung, J. Hebb, S. Sharma, C. Ni, J. Ren, J. Wen, J. H. Park, H. Chen, S. Chen, M. Hou, D. Tsai, J. Kuo, D. Liao, M. Chudzik, S. H. Lin, H. Huang, N. H. Yang, J. F. Lin, C. Tsai, G. Hung, S. Hsu, O. Cheng, J. Y. Wu, T. Yew
{"title":"Ultra low p-type SiGe contact resistance FinFETs with Ti silicide liner using cryogenic contact implantation amorphization and Solid-Phase Epitaxial Regrowth (SPER)","authors":"Y. R. Yang, N. Breil, C. Y. Yang, J. Hsieh, F. Chiang, B. Colombeau, B. Guo, K. Shim, N. Variam, G. Leung, J. Hebb, S. Sharma, C. Ni, J. Ren, J. Wen, J. H. Park, H. Chen, S. Chen, M. Hou, D. Tsai, J. Kuo, D. Liao, M. Chudzik, S. H. Lin, H. Huang, N. H. Yang, J. F. Lin, C. Tsai, G. Hung, S. Hsu, O. Cheng, J. Y. Wu, T. Yew","doi":"10.1109/VLSIT.2016.7573384","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573384","url":null,"abstract":"We report significant improvement of the TiSi / p-SiGe contact resistance by using a cryogenic (cold) boron implantation technique inside the contact trench of FinFET devices, providing both a source of dopants and a localized amorphization of the source/drain, self-aligned on the contact trench. A record low p-type contact resistivity of 5.9×10-9 ohm-cm2 is demonstrated and a 7.5% performance improvement is achieved. The variation of the implant temperature demonstrates a further improvement of the contact resistance when going to cryogenic (cold) implantation (-100°C). Using TCAD, we demonstrate that the reduced implant temperature provides a higher degree of amorphization and reduces defects. This is the key to provide an enhanced recrystallization of the doped amorphized region through Solid Phase Epitaxial Regrowth (SPER) low temperature activation. We propose in this paper a novel mechanism for p-type contacts, and demonstrate it for the first time on state-of-the-art FinFET p-type devices using cryogenic (cold) implants and SPER regrowth.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126258851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Te-based amorphous binary OTS device with excellent selector characteristics for x-point memory applications 基于te的非晶二元OTS器件,具有优异的选择特性,用于x点存储应用
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573389
Y. Koo, K. Baek, H. Hwang
{"title":"Te-based amorphous binary OTS device with excellent selector characteristics for x-point memory applications","authors":"Y. Koo, K. Baek, H. Hwang","doi":"10.1109/VLSIT.2016.7573389","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573389","url":null,"abstract":"We demonstrated binary Ovonic threshold switching (OTS) materials (ZnTe, GeTe, and SiTe) and the composition dependent electrical properties. Among those materials, amorphous SiTe-film deposited at room-temperature (RT) process showed excellent OTS properties such as high off resistance (~20GΩ at 0.2V), low on resistance (<;1kΩ at 1.2V), high selectivity (~106), extreme SS (<;1mV/dec), fast operating speed (2ns transition after 10ns delay), and good endurance (>500k cycles). In addition, the origin of the electronic switching of the binary OTS device was examined.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114766138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Selective GeOx-scavenging from interfacial layer on Si1−xGex channel for high mobility Si/Si1−xGex CMOS application 选择性清除Si1 - xGex通道上界面层的geox,用于高迁移率Si/Si1 - xGex CMOS应用
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573369
C. Lee, H. Kim, P. Jamison, R. Southwick, S. Mochizuki, K. Watanabe, R. Bao, R. Galatage, S. Guillaumet, T. Ando, R. Pandey, A. Konar, B. Lherron, J. Fronheiser, S. Siddiqui, H. Jagannathan, V. Paruchuri
{"title":"Selective GeOx-scavenging from interfacial layer on Si1−xGex channel for high mobility Si/Si1−xGex CMOS application","authors":"C. Lee, H. Kim, P. Jamison, R. Southwick, S. Mochizuki, K. Watanabe, R. Bao, R. Galatage, S. Guillaumet, T. Ando, R. Pandey, A. Konar, B. Lherron, J. Fronheiser, S. Siddiqui, H. Jagannathan, V. Paruchuri","doi":"10.1109/VLSIT.2016.7573369","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573369","url":null,"abstract":"We demonstrate a technique for selective GeO<sub>x</sub>-scavenging which creates a GeO<sub>x</sub>-free IL on Si<sub>1-x</sub>Ge<sub>x</sub> substrates. This process reduces N<sub>it</sub> by >60% to 2e11 and increases high-field mobility at N<sub>inv</sub>=1e13 cm<sup>-2</sup> by ~1.3× in Si<sub>0.6</sub>Ge<sub>0.4</sub> pFETs with sub-nm EOT.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123071842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Serially connected monolayer MoS2 FETs with channel patterned by a 7.5 nm resolution directed self-assembly lithography 具有7.5 nm分辨率定向自组装光刻通道的串联单层MoS2 fet
2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI: 10.1109/VLSIT.2016.7573376
A. Nourbakhsh, Ahmad Zubair, A. Tavakkoli, R. Sajjad, X. Ling, M. Dresselhaus, J. Kong, K. Berggren, D. Antoniadis, T. Palacios
{"title":"Serially connected monolayer MoS2 FETs with channel patterned by a 7.5 nm resolution directed self-assembly lithography","authors":"A. Nourbakhsh, Ahmad Zubair, A. Tavakkoli, R. Sajjad, X. Ling, M. Dresselhaus, J. Kong, K. Berggren, D. Antoniadis, T. Palacios","doi":"10.1109/VLSIT.2016.7573376","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573376","url":null,"abstract":"We demonstrate sub-10 nm transistor channel lengths by directed self-assembly patterning of monolayer MoS<sub>2</sub> in a periodic chain of homojunction semiconducting-(2H) and metallic-phase (1T') MoS<sub>2</sub> regions with half-pitch of 7.5 nm. The MoS<sub>2</sub> composite transistor possesses an off-state current of 100 pA/μm and an I<sub>on</sub>/I<sub>off</sub> ratio in excess of 10<sup>5</sup>. Modeling of the resulting current-voltage characteristics reveals that the 2H/1T' MoS<sub>2</sub> homojunction has a resistance of 75 Ω.μm while the 2H-MoS<sub>2</sub> exhibits low-field mobility of ~8 cm<sup>2</sup>/V.s and carrier injection velocity of ~10<sup>6</sup> cm/s.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122933606","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
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