L. Ragnarsson, H. Dekkers, P. Matagne, T. Schram, T. Conard, N. Horiguchi, A. Thean
{"title":"Zero-thickness multi work function solutions for N7 bulk FinFETs","authors":"L. Ragnarsson, H. Dekkers, P. Matagne, T. Schram, T. Conard, N. Horiguchi, A. Thean","doi":"10.1109/VLSIT.2016.7573393","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573393","url":null,"abstract":"A novel multi work function process is used to demonstrate up to 250 mV effective work function shifts of nMOS devices. The process use SiH4-soak of ALD TiN to change its barrier properties with ALD TiAl. FinFET devices are demonstrated with ~100 mV VT-shift for 24-nm-LG devices resulting in 20× reduction in off-state leakage at unaffected sub threshold slope and improved mismatch behavior. A patterning scheme using an nMOS first RMG process is proposed and demonstrated.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123272769","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Memory in the era of innovative architectures","authors":"Dean Klein","doi":"10.1109/VLSIT.2016.7573363","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573363","url":null,"abstract":"There is much buzz in the industry today about the “Post Moore's Law” state we are entering. Yet the opportunities for architectural innovation seem more prevalent than ever: 3D integration, advanced packaging solutions, specialized devices with specialized processes, new architectures and resiliency are just some areas of opportunity as we run out of an ability to scale in two dimensions.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128865582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Adusumilli, E. Alptekin, M. Raymond, N. Breil, F. Chafik, C. Lavoie, D. Ferrer, S. Jain, V. Kamineni, A. Ozcan, S. Allen, J. An, V. Basker, R. Bolam, H. Bu, J. Cai, J. Demarest, B. Doris, E. Engbrecht, S. Fan, J. Fronheiser, O. Gluschenkov, D. Guo, B. Haran, D. Hilscher, H. Jagannathan, D. Kang, Y. Ke, J. Kim, S. Koswatta, A. Kumar, A. Labonté, R. Lallement, W. Lee, Y. Lee, J. Li, C. Lin, B. Liu, Z. Liu, N. Loubet, N. Makela, S. Mochizuki, B. Morgenfeld, S. Narasimha, T. Nesheiwat, H. Niimi, C. Niu, M. Oh, C. Park, R. Ramachandran, J. Rice, V. Sardesai, J. Shearer, C. Sheraw, C. Tran, G. Tsutsui, H. Utomo, K. Wong, R. Xie, T. Yamashita, Y. Yan, C. Yeh, M. Yu, N. Zamdmer, N. Zhan, B. Zhang, V. Paruchuri, C. Goldberg, W. Kleemeier, S. Stiffler, R. Divakaruni, W. Henson
{"title":"Ti and NiPt/Ti liner silicide contacts for advanced technologies","authors":"P. Adusumilli, E. Alptekin, M. Raymond, N. Breil, F. Chafik, C. Lavoie, D. Ferrer, S. Jain, V. Kamineni, A. Ozcan, S. Allen, J. An, V. Basker, R. Bolam, H. Bu, J. Cai, J. Demarest, B. Doris, E. Engbrecht, S. Fan, J. Fronheiser, O. Gluschenkov, D. Guo, B. Haran, D. Hilscher, H. Jagannathan, D. Kang, Y. Ke, J. Kim, S. Koswatta, A. Kumar, A. Labonté, R. Lallement, W. Lee, Y. Lee, J. Li, C. Lin, B. Liu, Z. Liu, N. Loubet, N. Makela, S. Mochizuki, B. Morgenfeld, S. Narasimha, T. Nesheiwat, H. Niimi, C. Niu, M. Oh, C. Park, R. Ramachandran, J. Rice, V. Sardesai, J. Shearer, C. Sheraw, C. Tran, G. Tsutsui, H. Utomo, K. Wong, R. Xie, T. Yamashita, Y. Yan, C. Yeh, M. Yu, N. Zamdmer, N. Zhan, B. Zhang, V. Paruchuri, C. Goldberg, W. Kleemeier, S. Stiffler, R. Divakaruni, W. Henson","doi":"10.1109/VLSIT.2016.7573382","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573382","url":null,"abstract":"We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124674708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Vasen, P. Ramvall, A. Afzalian, C. Thelander, K. Dick, M. Holland, G. Doornbos, S. W. Wang, R. Oxland, G. Vellianitis, M. V. van Dal, B. Duriez, J. Ramírez, R. Droopad, L. Wernersson, L. Samuelson, T.K. Chen, Y. Yeo, M. Passlack
{"title":"InAs nanowire GAA n-MOSFETs with 12–15 nm diameter","authors":"T. Vasen, P. Ramvall, A. Afzalian, C. Thelander, K. Dick, M. Holland, G. Doornbos, S. W. Wang, R. Oxland, G. Vellianitis, M. V. van Dal, B. Duriez, J. Ramírez, R. Droopad, L. Wernersson, L. Samuelson, T.K. Chen, Y. Yeo, M. Passlack","doi":"10.1109/VLSIT.2016.7573417","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573417","url":null,"abstract":"InAs nanowires (NW) grown by MOCVD with diameter d as small as 10 nm and gate-all-around (GAA) MOSFETs with d = 12-15 nm are demonstrated. I<sub>on</sub> = 314 μA/μm, and S<sub>sat</sub> =68 mV/dec was achieved at V<sub>dd</sub> = 0.5 V (I<sub>off</sub> = 0.1 μA/μm). Highest g<sub>m</sub> measured is 2693 μS/μm. Device performance is enabled by small diameter and optimized high-k/InAs gate stack process. Device performance tradeoffs between g<sub>m</sub>, R<sub>on</sub>, and I<sub>min</sub> are discussed.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"418 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115995290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Changsik Shin, Wonji Lee, Sewon Lee, Byeongho Jeong, Jongmin Lee, Unyong Jang, Yong-Goo Kim, Sang-Han Lee, Jun-Suk Bang, G. Cho
{"title":"A sine-reference band (SRB)-controlled average current technique for a phase-cut dimmable AC-DC buck LED driver without an electrolytic capacitor","authors":"Changsik Shin, Wonji Lee, Sewon Lee, Byeongho Jeong, Jongmin Lee, Unyong Jang, Yong-Goo Kim, Sang-Han Lee, Jun-Suk Bang, G. Cho","doi":"10.1109/VLSIT.2016.7573397","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573397","url":null,"abstract":"A phase-cut dimmable AC-DC buck LED driver is presented with a sine-reference band (SRB)-controlled average current technique as a new control scheme. The proposed SRB-controlled average current technique can perform both sine current control and phase dimming control. The sine current control regulates the average LED current as a sine-wave maintaining high power factor. The phase dimming control removes visible flicker at AC line frequency without an electrolytic capacitor and makes the driver compatible with two types of phase-cut dimmer. Experimental results show line regulation <; ±2.4% (90-260Vac), load regulation <; ±0.7% (10-36 LEDs), PF > 0.95, and 90.7% peak efficiency.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127059359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Hashemi, T. Ando, K. Balakrishnan, E. Cartier, M. Lofaro, J. Ott, J. Bruley, K. Lee, S. Koswatta, S. Dawes, J. Rozen, A. Pyzyna, K. Chan, S. Engelmann, D. Park, V. Narayanan, R. Mo, E. Leobandung
{"title":"Replacement high-K/metal-gate High-Ge-content strained SiGe FinFETs with high hole mobility and excellent SS and reliability at aggressive EOT ∼7Å and scaled dimensions down to sub-4nm fin widths","authors":"P. Hashemi, T. Ando, K. Balakrishnan, E. Cartier, M. Lofaro, J. Ott, J. Bruley, K. Lee, S. Koswatta, S. Dawes, J. Rozen, A. Pyzyna, K. Chan, S. Engelmann, D. Park, V. Narayanan, R. Mo, E. Leobandung","doi":"10.1109/VLSIT.2016.7573392","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573392","url":null,"abstract":"High-Ge-content (HGC) SiGe FinFETs in a “replacement High-K and metal-gate” (RMG) process flow and with aggressive EOT scaling are demonstrated, for the first time. HGC SiGe pMOS FinFETs with high-mobility, record-low RMG long-channel SS=66mV/dec and great short-channel characteristics down to L<sub>G</sub>=21nm have been demonstrated. Gate stack and transport properties down to sub-4nm fin widths (W<sub>FIN</sub>) have been also studied for the first time. We demonstrate excellent RMG mobility and reliability at aggressive EOT~7Å, and excellent μ<sub>eff</sub>=220cm<sup>2</sup>/Vs at N<sub>inv</sub>=10<sup>13</sup> for fins with W<sub>FIN</sub>~4nm, outperforming state-of-the-art devices at such dimensions and providing very promising results for FinFET scaling for future high-performance FinFET generations.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127266983","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Hutin, R. Maurand, D. Kotekar-Patil, A. Corna, H. Bohuslavskyi, X. Jehl, S. Barraud, S. de Franceschi, M. Sanquer, M. Vinet
{"title":"Si CMOS platform for quantum information processing","authors":"L. Hutin, R. Maurand, D. Kotekar-Patil, A. Corna, H. Bohuslavskyi, X. Jehl, S. Barraud, S. de Franceschi, M. Sanquer, M. Vinet","doi":"10.1109/VLSIT.2016.7573380","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573380","url":null,"abstract":"We report the first quantum bit (qubit) device implemented on a foundry-compatible Si CMOS platform. The device, fabricated using SOI NanoWire MOSFET technology, is in essence a compact two-gate pFET. The qubit is encoded in the spin degree of freedom of a hole Quantum Dot (QD) defined by one of the Gates. Coherent spin manipulation is performed by means of an RF E-Field signal applied to the Gate itself. By demonstrating qubit functionality in a conventional transistor-like layout and process flow, this result bears relevance for the future up-scaling of qubit architectures, including the opportunity of their co-integration with “classical” Si CMOS control circuitry.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128010115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Dongaonkar, M. Giles, A. Kornfeld, B. Grossnickle, J. Yoon
{"title":"Random telegraph noise (RTN) in 14nm logic technology: High volume data extraction and analysis","authors":"S. Dongaonkar, M. Giles, A. Kornfeld, B. Grossnickle, J. Yoon","doi":"10.1109/VLSIT.2016.7573424","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573424","url":null,"abstract":"With continued scaling of CMOS technology, numerous concerns have been raised about random telegraph noise (RTN) possibly matching or exceeding the random process variation in threshold voltage (Vth)[1], [2]. These studies are usually limited by the small sample size of the measurements, relying on modeling for projecting to high sigma. In this work, we use a modified ring oscillator (RO) circuit to measure the RTN in individual transistors (7500 NMOS and 7500 PMOS), for Intel's current 14nm technology. We analyze this data, carefully characterizing the noise signatures and accounting for the devices not showing RTN. We show that magnitude of Vth fluctuation due to RTN (ΔVthRTN) at the ~3.7 sigma level is <; 25mV, and the ΔVthRTN is uncorrelated to Vth random variation. From these observations, we conclude that RTN is not a significant limitation for circuit design at Intel's 14nm node.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133071582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Z. Tokei, I. Ciofi, P. Roussel, P. Debacker, P. Raghavan, M. H. van der Veen, N. Jourdan, C. Wilson, V. V. Gonzalez, C. Adelmann, L. Wen, K. Croes, O. V. P. K. Moors, M. Krishtab, S. Armini, J. Bommels
{"title":"On-chip interconnect trends, challenges and solutions: How to keep RC and reliability under control","authors":"Z. Tokei, I. Ciofi, P. Roussel, P. Debacker, P. Raghavan, M. H. van der Veen, N. Jourdan, C. Wilson, V. V. Gonzalez, C. Adelmann, L. Wen, K. Croes, O. V. P. K. Moors, M. Krishtab, S. Armini, J. Bommels","doi":"10.1109/VLSIT.2016.7573426","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573426","url":null,"abstract":"Interconnects pose increasing challenges as technology scaling proceeds. In order to overcome these challenges simultaneous optimization of novel metallization schemes, new materials, circuit and system level approaches are required.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122673479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Ren, R. Gao, Z. Ji, H. Arimura, J. F. Zhang, R. Wang, M. Duan, W. Zhang, J. Franco, S. Sioncke, D. Cott, J. Mitard, L. Witters, H. Mertens, B. Kaczer, A. Mocuta, N. Collaert, D. Linten, R. Huang, A. Thean, G. Groeseneken
{"title":"Understanding charge traps for optimizing Si-passivated Ge nMOSFETs","authors":"P. Ren, R. Gao, Z. Ji, H. Arimura, J. F. Zhang, R. Wang, M. Duan, W. Zhang, J. Franco, S. Sioncke, D. Cott, J. Mitard, L. Witters, H. Mertens, B. Kaczer, A. Mocuta, N. Collaert, D. Linten, R. Huang, A. Thean, G. Groeseneken","doi":"10.1109/VLSIT.2016.7573367","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573367","url":null,"abstract":"For the first time, two different types of electron traps are clearly identified in Ge nFETs with Type-A controlled by the HfO2 layer thickness and Type-B by the Si growth induced Ge segregation. Only Type-B are responsible for mobility degradation and they do not saturate with stress time, while the opposite applies to Type A. A PBTI model is proposed and validated for the long term prediction.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128374410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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