A. Laurent, X. Garros, S. Barraud, G. Mariniello, G. Reimbold, D. Roy, E. Vincent, G. Ghibaudo
{"title":"Hot carrier degradation in nanowire transistors: Physical mechanisms, width dependence and impact of Self-Heating","authors":"A. Laurent, X. Garros, S. Barraud, G. Mariniello, G. Reimbold, D. Roy, E. Vincent, G. Ghibaudo","doi":"10.1109/VLSIT.2016.7573374","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573374","url":null,"abstract":"We present an extensive study of Hot Carrier reliability in N-Ωfet nanowires. For the first time 3 HC degradation modes were clearly evidenced as in planar technology and accurately modeled. Moreover HC reliability was proved to be width-independent. Finally it is shown that, although SH is important in nanowires, it has almost no implication on its HC reliability because of the weak temperature dependence of the HC mechanisms.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127412610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Lung, Y. Ho, Y. Zhu, W. Chien, S. Kim, W. Kim, H. Cheng, A. Ray, M. BrightSky, R. Bruce, C. Yeh, C. Lam
{"title":"A novel low power phase change memory using inter-granular switching","authors":"H. Lung, Y. Ho, Y. Zhu, W. Chien, S. Kim, W. Kim, H. Cheng, A. Ray, M. BrightSky, R. Bruce, C. Yeh, C. Lam","doi":"10.1109/VLSIT.2016.7573405","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573405","url":null,"abstract":"We propose and demonstrate a new low power phase change memory using a novel 3D network of crystallites with phase change confined to only at grain intersections. Contrary to conventional phase change memories, for which an entire volume of chalcogenide glass is amorphized or crystallized for high or low resistance, we propose a multi-grained structure where we only induce phase change in the inter-grain regions. This not only drastically reduces the phase change volume but also improves the thermal efficiency of the cell. 3D simulation is used to understand the local heating effect. To create the multi-grained structure we have carefully studied the Ge/Sb/Te composition, the doping material and concentration and PVD deposition conditions. Consequently, the switching current can be reduced to 20uA. Furthermore, localizing the heating also reduces thermal disturbance to neighboring cells thus provides excellent pitch scalability.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125358436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shao Hui Wu, X. Y. Jia, Mei Kui, C. Shuai, Tien-Yu Hsieh, H. Lin, Derek Chen, Chen Bin Lin, J. Y. Wu, T. Yew, Yuta Endo, K. Kato, S. Yamazaki
{"title":"Extremely low power c-axis aligned crystalline In-Ga-Zn-O 60 nm transistor integrated with industry 65 nm Si MOSFET for IoT normally-off CPU application","authors":"Shao Hui Wu, X. Y. Jia, Mei Kui, C. Shuai, Tien-Yu Hsieh, H. Lin, Derek Chen, Chen Bin Lin, J. Y. Wu, T. Yew, Yuta Endo, K. Kato, S. Yamazaki","doi":"10.1109/VLSIT.2016.7573378","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573378","url":null,"abstract":"For the first time, laboratory 60 nm c-axis aligned crystalline In-Ga-Zn-O (CAAC-IGZO) oxide semiconductor FET (OSFET) was successfully integrated with industrial 65 nm Si MOSFET (SiFET). By this hybrid process, OSFET with extremely low off-state leakage level ~zA (1×10-21A) was fabricated, while traditional Si device can only reach 1×10-12A leakage level. For IoT (Internet of Things) applications, normally-off CPU (Noff CPU) fabricated by this hybrid process achieved 86% reduction of power consumption. The hybrid process can be extended to other applications like eDRAM, image sensor and FPGA.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116796009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. A. Sharma, Y. Kesim, M. Shulaker, C. Kuo, C. Augustine, H. Wong, S. Mitra, M. Skowronski, J. Bain, J. Weldon
{"title":"Low-power, high-performance S-NDR oscillators for stereo (3D) vision using directly-coupled oscillator networks","authors":"A. A. Sharma, Y. Kesim, M. Shulaker, C. Kuo, C. Augustine, H. Wong, S. Mitra, M. Skowronski, J. Bain, J. Weldon","doi":"10.1109/VLSIT.2016.7573438","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573438","url":null,"abstract":"We have successfully demonstrated, a best in class low-power, high-performance S-NDR oscillator (benchmarked in Table I) through novel & unique material-engineering of leakage, endurance and by improving SNR through parallel-locking. These oscillators were then connected in form of a dense array that utilized unique array properties to simulate a full stereo-vision system. The system was found to consume 100× lower energy while being 16× better in performance (Table II), when compared to a conventional implementation purely based on computation.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131138671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Cho, H. Oh, K. Nam, Y. H. Kim, K. Yeo, W. D. Kim, Y. Chung, Y. Nam, S. M. Kim, W. Kwon, M. Kang, I. Kim, H. Fukutome, C. Jeong, H. J. Shin, Y. S. Kim, D. Kim, S. H. Park, J. Jeong, S. Kim, D. Ha, J. Park, H. Rhee, S. Hyun, D. Shin, D. H. Kim, H. Y. Kim, S. Maeda, K. H. Lee, M. Kim, Y. Koh, B. Yoon, K. Shin, N. Lee, S. KangH., K. Hwang, J. Lee, J. Ku, S. Nam, S. M. Jung, H. K. Kang, J. S. Yoon, E. Jung
{"title":"Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications","authors":"H. Cho, H. Oh, K. Nam, Y. H. Kim, K. Yeo, W. D. Kim, Y. Chung, Y. Nam, S. M. Kim, W. Kwon, M. Kang, I. Kim, H. Fukutome, C. Jeong, H. J. Shin, Y. S. Kim, D. Kim, S. H. Park, J. Jeong, S. Kim, D. Ha, J. Park, H. Rhee, S. Hyun, D. Shin, D. H. Kim, H. Y. Kim, S. Maeda, K. H. Lee, M. Kim, Y. Koh, B. Yoon, K. Shin, N. Lee, S. KangH., K. Hwang, J. Lee, J. Ku, S. Nam, S. M. Jung, H. K. Kang, J. S. Yoon, E. Jung","doi":"10.1109/VLSIT.2016.7573359","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573359","url":null,"abstract":"10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122321734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Okamoto, M. Tada, N. Banno, N. Iguchi, H. Hada, T. Sakamoto, M. Miyamura, Y. Tsuji, R. Nebashi, A. Morioka, X. Bai, T. Sugibayashi
{"title":"Robust Cu atom switch with over-400°C thermally tolerant polymer-solid electrolyte (TT-PSE) for nonvolatile programmable logic","authors":"K. Okamoto, M. Tada, N. Banno, N. Iguchi, H. Hada, T. Sakamoto, M. Miyamura, Y. Tsuji, R. Nebashi, A. Morioka, X. Bai, T. Sugibayashi","doi":"10.1109/VLSIT.2016.7573403","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573403","url":null,"abstract":"A fully 400°C-processed, standard Cu-BEOL compatible, robust Cu atom switch has been developed featuring an over-400°C high thermally tolerant polymer-solid electrolyte (TT-PSE). Hydrocarbons that have weak chemical bindings in the PSE are selectively eliminated in the TT-PSE, resulting in higher thermal stability. The TT-PSE also gives higher breakdown voltage (+1V) with keeping low set voltage (2V) due to the elimination of the fragile hydrocarbon bindings. Data retention characteristics after thermal cycle stress at temperature ranging from -65 to 150°C for 1000 cycles are confirmed for the first time. The developed atom switch is to be a technology enabler of reliable reprogrammable logics for future robotic/vehicle applications at high temperatures.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129043168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
O. Weber, E. Josse, X. Garros, M. Rafik, X. Federspiel, C. Diouf, A. Toffoli, S. Zoll, O. Gourhant, V. Joseph, C. Suarez-Segovia, F. Domengie, V. Beugin, B. Saidi, M. Gros-Jean, P. Perreau, J. Mazurier, E. Richard, M. Haond
{"title":"Gate stack solutions in gate-first FDSOI technology to meet high performance, low leakage, VT centering and reliability criteria","authors":"O. Weber, E. Josse, X. Garros, M. Rafik, X. Federspiel, C. Diouf, A. Toffoli, S. Zoll, O. Gourhant, V. Joseph, C. Suarez-Segovia, F. Domengie, V. Beugin, B. Saidi, M. Gros-Jean, P. Perreau, J. Mazurier, E. Richard, M. Haond","doi":"10.1109/VLSIT.2016.7573434","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573434","url":null,"abstract":"A unique gate stack solution has been found in gate-first FDSOI to meet at the same time high performance, low leakage, V<sub>T</sub> centering and reliability criteria for NMOS and PMOS with T<sub>inv</sub>=12.5Å and 14Å, respectively. Trade-offs between those characteristics are highlighted in this paper through process knob variations, including the interfacial layer (IL) formation, the IL surface treatment and the drive-in anneal temperature. The path allowing the construction of both low-V<sub>T</sub> high speed logic, reaching 7.2ps/stg FO3 ring oscillator delay at V<sub>nom</sub>=0.8V, and high-V<sub>T</sub> low leakage SRAM, achieving 3pA/cell standby leakage at V<sub>nom</sub>=0.8V, is demonstrated through gate workfunction engineering and gate leakage optimization. On top of this result, 5 years BTI and 10 years TDDB reliability lifetime were qualified at V<sub>max</sub>=0.945V, 125°C.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129132536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hiroki Takahashi, Hiroshi Tanaka, M. Oda, Mitsuyoshi Ando, N. Niisoe, S. Kawai, Takuya Asano, Minoru Sudo, M. Yoshita, Tohru Yamada
{"title":"Novel pixel structure with Stacked Deep Photodiode to achieve high NIR sensitivity and high MTF","authors":"Hiroki Takahashi, Hiroshi Tanaka, M. Oda, Mitsuyoshi Ando, N. Niisoe, S. Kawai, Takuya Asano, Minoru Sudo, M. Yoshita, Tohru Yamada","doi":"10.1109/VLSIT.2016.7573450","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573450","url":null,"abstract":"Novel pixel structure with Stacked Deep Photodiode (SDP) has been newly developed for both high Near Infra-Red (NIR) sensitivity and high Modulation Transfer Function (MTF). SDP with 5.4μm pixel pitch has achieved Quantum Efficiency (QE) of 30% and MTF of 40% at Nyquist frequency at 850nm wavelength by stacking photodiode completely separated from neighboring pixels.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129243077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yu-Chieh Huang, Yu-Chen Hu, Po-Tsang Huang, Shang-Lin Wu, Y. You, Jr-Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, J. Duann, Tzai-Wen Chiu, W. Hwang, C. Chuang, J. Chiou, Kuan-Neng Chen
{"title":"Integration of neural sensing microsystem with TSV-embedded dissolvable µ-needles array, biocompatible flexible interposer, and neural recording circuits","authors":"Yu-Chieh Huang, Yu-Chen Hu, Po-Tsang Huang, Shang-Lin Wu, Y. You, Jr-Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, J. Duann, Tzai-Wen Chiu, W. Hwang, C. Chuang, J. Chiou, Kuan-Neng Chen","doi":"10.1109/VLSIT.2016.7573441","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573441","url":null,"abstract":"Local brain connectivity is expected to lead to new models for neurological diseases, which may in turn result in advanced understanding and better treatment. This paper presents a neural sensing microsystem integrated with TSV-embedded dissolvable μ-needles array, ENIG bonding technology, biocompatible Au-TSV flexible interposer and neural recording circuits, for neural sensing implantation. An ultra-thin film bonding approach is proposed for integration of interposer assembly. Removing bonding wire by proposed bonding technology, the dimension of neural sensing system can be minimized to reduce surgical area and promote implant success rate. The signal quality of neural recording can be significantly improved by eliminating complex signal paths with 2.5D TSV integration from neural sensing interface to neural recording circuits.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114476102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Mertens, R. Ritzenthaler, A. Hikavyy, M. Kim, Z. Tao, K. Wostyn, S. Chew, A. De Keersgieter, G. Mannaert, E. Rosseel, T. Schram, K. Devriendt, D. Tsvetanova, H. Dekkers, S. Demuynck, A. Chasin, E. Van Besien, A. Dangol, S. Godny, B. Douhard, N. Bosman, O. Richard, J. Geypen, H. Bender, K. Barla, D. Mocuta, N. Horiguchi, A. Thean
{"title":"Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates","authors":"H. Mertens, R. Ritzenthaler, A. Hikavyy, M. Kim, Z. Tao, K. Wostyn, S. Chew, A. De Keersgieter, G. Mannaert, E. Rosseel, T. Schram, K. Devriendt, D. Tsvetanova, H. Dekkers, S. Demuynck, A. Chasin, E. Van Besien, A. Dangol, S. Godny, B. Douhard, N. Bosman, O. Richard, J. Geypen, H. Bender, K. Barla, D. Mocuta, N. Horiguchi, A. Thean","doi":"10.1109/VLSIT.2016.7573416","DOIUrl":"https://doi.org/10.1109/VLSIT.2016.7573416","url":null,"abstract":"We report on gate-all-around (GAA) n- and p-MOSFETs made of 8-nm-diameter vertically stacked horizontal Si nanowires (NWs). We show that these devices, which were fabricated on bulk Si substrates using an industry-relevant replacement metal gate (RMG) process, have excellent short-channel characteristics (SS = 65 mV/dec, DIBL = 42 mV/V for LG = 24 nm) at performance levels comparable to finFET reference devices. The parasitic channels below the Si NWs were effectively suppressed by ground plane (GP) engineering.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133403337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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