Gate stack solutions in gate-first FDSOI technology to meet high performance, low leakage, VT centering and reliability criteria

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI:10.1109/VLSIT.2016.7573434

O. Weber, E. Josse, X. Garros, M. Rafik, X. Federspiel, C. Diouf, A. Toffoli, S. Zoll, O. Gourhant, V. Joseph, C. Suarez-Segovia, F. Domengie, V. Beugin, B. Saidi, M. Gros-Jean, P. Perreau, J. Mazurier, E. Richard, M. Haond

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引用次数: 2

Abstract

A unique gate stack solution has been found in gate-first FDSOI to meet at the same time high performance, low leakage, V_T centering and reliability criteria for NMOS and PMOS with T_inv=12.5Å and 14Å, respectively. Trade-offs between those characteristics are highlighted in this paper through process knob variations, including the interfacial layer (IL) formation, the IL surface treatment and the drive-in anneal temperature. The path allowing the construction of both low-V_T high speed logic, reaching 7.2ps/stg FO3 ring oscillator delay at V_nom=0.8V, and high-V_T low leakage SRAM, achieving 3pA/cell standby leakage at V_nom=0.8V, is demonstrated through gate workfunction engineering and gate leakage optimization. On top of this result, 5 years BTI and 10 years TDDB reliability lifetime were qualified at V_max=0.945V, 125°C.

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栅极堆栈解决方案采用栅极优先FDSOI技术，满足高性能、低泄漏、VT定心和可靠性标准

为满足Tinv=12.5Å和14Å的NMOS和PMOS的高性能、低泄漏、VT定心和可靠性标准，在栅极优先FDSOI中找到了一种独特的栅极堆栈解决方案。本文通过工艺旋钮变化强调了这些特性之间的权衡，包括界面层(IL)形成，IL表面处理和驱动退火温度。通过栅极工作函数工程和栅极漏电优化，展示了在Vnom=0.8V时实现7.2ps/stg的低vt高速逻辑和在Vnom=0.8V时实现3pA/cell待机漏电的高vt低漏电SRAM的构建路径。在此结果的基础上，在Vmax=0.945V, 125°C时，5年BTI和10年TDDB可靠性寿命合格。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2016 IEEE Symposium on VLSI Technology

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