Extremely low power c-axis aligned crystalline In-Ga-Zn-O 60 nm transistor integrated with industry 65 nm Si MOSFET for IoT normally-off CPU application
Shao Hui Wu, X. Y. Jia, Mei Kui, C. Shuai, Tien-Yu Hsieh, H. Lin, Derek Chen, Chen Bin Lin, J. Y. Wu, T. Yew, Yuta Endo, K. Kato, S. Yamazaki
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引用次数: 13
Abstract
For the first time, laboratory 60 nm c-axis aligned crystalline In-Ga-Zn-O (CAAC-IGZO) oxide semiconductor FET (OSFET) was successfully integrated with industrial 65 nm Si MOSFET (SiFET). By this hybrid process, OSFET with extremely low off-state leakage level ~zA (1×10-21A) was fabricated, while traditional Si device can only reach 1×10-12A leakage level. For IoT (Internet of Things) applications, normally-off CPU (Noff CPU) fabricated by this hybrid process achieved 86% reduction of power consumption. The hybrid process can be extended to other applications like eDRAM, image sensor and FPGA.
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