H. Cho, H. Oh, K. Nam, Y. H. Kim, K. Yeo, W. D. Kim, Y. Chung, Y. Nam, S. M. Kim, W. Kwon, M. Kang, I. Kim, H. Fukutome, C. Jeong, H. J. Shin, Y. S. Kim, D. Kim, S. H. Park, J. Jeong, S. Kim, D. Ha, J. Park, H. Rhee, S. Hyun, D. Shin, D. H. Kim, H. Y. Kim, S. Maeda, K. H. Lee, M. Kim, Y. Koh, B. Yoon, K. Shin, N. Lee, S. KangH., K. Hwang, J. Lee, J. Ku, S. Nam, S. M. Jung, H. K. Kang, J. S. Yoon, E. Jung
{"title":"Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications","authors":"H. Cho, H. Oh, K. Nam, Y. H. Kim, K. Yeo, W. D. Kim, Y. Chung, Y. Nam, S. M. Kim, W. Kwon, M. Kang, I. Kim, H. Fukutome, C. Jeong, H. J. Shin, Y. S. Kim, D. Kim, S. H. Park, J. Jeong, S. Kim, D. Ha, J. Park, H. Rhee, S. Hyun, D. Shin, D. H. Kim, H. Y. Kim, S. Maeda, K. H. Lee, M. Kim, Y. Koh, B. Yoon, K. Shin, N. Lee, S. KangH., K. Hwang, J. Lee, J. Ku, S. Nam, S. M. Jung, H. K. Kang, J. S. Yoon, E. Jung","doi":"10.1109/VLSIT.2016.7573359","DOIUrl":null,"url":null,"abstract":"10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"181 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"54","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573359","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 54
Abstract
10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.
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