O. Weber, E. Josse, X. Garros, M. Rafik, X. Federspiel, C. Diouf, A. Toffoli, S. Zoll, O. Gourhant, V. Joseph, C. Suarez-Segovia, F. Domengie, V. Beugin, B. Saidi, M. Gros-Jean, P. Perreau, J. Mazurier, E. Richard, M. Haond
{"title":"栅极堆栈解决方案采用栅极优先FDSOI技术，满足高性能、低泄漏、VT定心和可靠性标准","authors":"O. Weber, E. Josse, X. Garros, M. Rafik, X. Federspiel, C. Diouf, A. Toffoli, S. Zoll, O. Gourhant, V. Joseph, C. Suarez-Segovia, F. Domengie, V. Beugin, B. Saidi, M. Gros-Jean, P. Perreau, J. Mazurier, E. Richard, M. Haond","doi":"10.1109/VLSIT.2016.7573434","DOIUrl":null,"url":null,"abstract":"A unique gate stack solution has been found in gate-first FDSOI to meet at the same time high performance, low leakage, V<sub>T</sub> centering and reliability criteria for NMOS and PMOS with T<sub>inv</sub>=12.5Å and 14Å, respectively. Trade-offs between those characteristics are highlighted in this paper through process knob variations, including the interfacial layer (IL) formation, the IL surface treatment and the drive-in anneal temperature. The path allowing the construction of both low-V<sub>T</sub> high speed logic, reaching 7.2ps/stg FO3 ring oscillator delay at V<sub>nom</sub>=0.8V, and high-V<sub>T</sub> low leakage SRAM, achieving 3pA/cell standby leakage at V<sub>nom</sub>=0.8V, is demonstrated through gate workfunction engineering and gate leakage optimization. On top of this result, 5 years BTI and 10 years TDDB reliability lifetime were qualified at V<sub>max</sub>=0.945V, 125°C.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Gate stack solutions in gate-first FDSOI technology to meet high performance, low leakage, VT centering and reliability criteria\",\"authors\":\"O. Weber, E. Josse, X. Garros, M. Rafik, X. Federspiel, C. Diouf, A. Toffoli, S. Zoll, O. Gourhant, V. Joseph, C. Suarez-Segovia, F. Domengie, V. Beugin, B. Saidi, M. Gros-Jean, P. Perreau, J. Mazurier, E. Richard, M. Haond\",\"doi\":\"10.1109/VLSIT.2016.7573434\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A unique gate stack solution has been found in gate-first FDSOI to meet at the same time high performance, low leakage, V<sub>T</sub> centering and reliability criteria for NMOS and PMOS with T<sub>inv</sub>=12.5Å and 14Å, respectively. Trade-offs between those characteristics are highlighted in this paper through process knob variations, including the interfacial layer (IL) formation, the IL surface treatment and the drive-in anneal temperature. The path allowing the construction of both low-V<sub>T</sub> high speed logic, reaching 7.2ps/stg FO3 ring oscillator delay at V<sub>nom</sub>=0.8V, and high-V<sub>T</sub> low leakage SRAM, achieving 3pA/cell standby leakage at V<sub>nom</sub>=0.8V, is demonstrated through gate workfunction engineering and gate leakage optimization. On top of this result, 5 years BTI and 10 years TDDB reliability lifetime were qualified at V<sub>max</sub>=0.945V, 125°C.\",\"PeriodicalId\":129300,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Technology\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2016.7573434\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573434","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Gate stack solutions in gate-first FDSOI technology to meet high performance, low leakage, VT centering and reliability criteria
A unique gate stack solution has been found in gate-first FDSOI to meet at the same time high performance, low leakage, VT centering and reliability criteria for NMOS and PMOS with Tinv=12.5Å and 14Å, respectively. Trade-offs between those characteristics are highlighted in this paper through process knob variations, including the interfacial layer (IL) formation, the IL surface treatment and the drive-in anneal temperature. The path allowing the construction of both low-VT high speed logic, reaching 7.2ps/stg FO3 ring oscillator delay at Vnom=0.8V, and high-VT low leakage SRAM, achieving 3pA/cell standby leakage at Vnom=0.8V, is demonstrated through gate workfunction engineering and gate leakage optimization. On top of this result, 5 years BTI and 10 years TDDB reliability lifetime were qualified at Vmax=0.945V, 125°C.
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