Ti and NiPt/Ti liner silicide contacts for advanced technologies

2016 IEEE Symposium on VLSI Technology Pub Date : 2016-06-14 DOI:10.1109/VLSIT.2016.7573382

P. Adusumilli, E. Alptekin, M. Raymond, N. Breil, F. Chafik, C. Lavoie, D. Ferrer, S. Jain, V. Kamineni, A. Ozcan, S. Allen, J. An, V. Basker, R. Bolam, H. Bu, J. Cai, J. Demarest, B. Doris, E. Engbrecht, S. Fan, J. Fronheiser, O. Gluschenkov, D. Guo, B. Haran, D. Hilscher, H. Jagannathan, D. Kang, Y. Ke, J. Kim, S. Koswatta, A. Kumar, A. Labonté, R. Lallement, W. Lee, Y. Lee, J. Li, C. Lin, B. Liu, Z. Liu, N. Loubet, N. Makela, S. Mochizuki, B. Morgenfeld, S. Narasimha, T. Nesheiwat, H. Niimi, C. Niu, M. Oh, C. Park, R. Ramachandran, J. Rice, V. Sardesai, J. Shearer, C. Sheraw, C. Tran, G. Tsutsui, H. Utomo, K. Wong, R. Xie, T. Yamashita, Y. Yan, C. Yeh, M. Yu, N. Zamdmer, N. Zhan, B. Zhang, V. Paruchuri, C. Goldberg, W. Kleemeier, S. Stiffler, R. Divakaruni, W. Henson

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引用次数: 20

Abstract

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

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Ti和NiPt/Ti衬里硅化触头先进技术

我们讨论了从14nm及以上节点开始的3D FinFET器件的源极漏极(SD)触点向Ti基硅化物的过渡。随着金属化工艺和掺杂剂浓度的优化，n-FET和p-FET的接触电阻有所降低。发现SiGe外延的优化和薄界面NiPt(10%)的添加显著改善了p-FET的接触性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2016 IEEE Symposium on VLSI Technology

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