Z. Tokei, I. Ciofi, P. Roussel, P. Debacker, P. Raghavan, M. H. van der Veen, N. Jourdan, C. Wilson, V. V. Gonzalez, C. Adelmann, L. Wen, K. Croes, O. V. P. K. Moors, M. Krishtab, S. Armini, J. Bommels
{"title":"片上互连趋势、挑战和解决方案:如何控制RC和可靠性","authors":"Z. Tokei, I. Ciofi, P. Roussel, P. Debacker, P. Raghavan, M. H. van der Veen, N. Jourdan, C. Wilson, V. V. Gonzalez, C. Adelmann, L. Wen, K. Croes, O. V. P. K. Moors, M. Krishtab, S. Armini, J. Bommels","doi":"10.1109/VLSIT.2016.7573426","DOIUrl":null,"url":null,"abstract":"Interconnects pose increasing challenges as technology scaling proceeds. In order to overcome these challenges simultaneous optimization of novel metallization schemes, new materials, circuit and system level approaches are required.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"On-chip interconnect trends, challenges and solutions: How to keep RC and reliability under control\",\"authors\":\"Z. Tokei, I. Ciofi, P. Roussel, P. Debacker, P. Raghavan, M. H. van der Veen, N. Jourdan, C. Wilson, V. V. Gonzalez, C. Adelmann, L. Wen, K. Croes, O. V. P. K. Moors, M. Krishtab, S. Armini, J. Bommels\",\"doi\":\"10.1109/VLSIT.2016.7573426\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Interconnects pose increasing challenges as technology scaling proceeds. In order to overcome these challenges simultaneous optimization of novel metallization schemes, new materials, circuit and system level approaches are required.\",\"PeriodicalId\":129300,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Technology\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2016.7573426\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573426","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On-chip interconnect trends, challenges and solutions: How to keep RC and reliability under control
Interconnects pose increasing challenges as technology scaling proceeds. In order to overcome these challenges simultaneous optimization of novel metallization schemes, new materials, circuit and system level approaches are required.