X. Zhou, N. Waldron, G. Boccardi, F. Sebaai, C. Merckling, G. Eneman, S. Sioncke, L. Nyns, A. Opdebeeck, J. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, W. Guo, B. Kunert, L. Teugels, K. Devriendt, A. S. Hernandez, J. Franco, D. V. van Dorp, K. Barla, N. Collaert, A. Thean
{"title":"在300mm Si平台上集成InGaAs栅极全能场效应管的可扩展性:通道宽度降至7nm, Lg降至36nm的演示","authors":"X. Zhou, N. Waldron, G. Boccardi, F. Sebaai, C. Merckling, G. Eneman, S. Sioncke, L. Nyns, A. Opdebeeck, J. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, W. Guo, B. Kunert, L. Teugels, K. Devriendt, A. S. Hernandez, J. Franco, D. V. van Dorp, K. Barla, N. Collaert, A. Thean","doi":"10.1109/VLSIT.2016.7573420","DOIUrl":null,"url":null,"abstract":"We report In<sub>0.53</sub>GaAs-channel gate-all-around FETs with channel width down to 7nm and L<sub>g</sub> down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g<sub>m</sub> by 25% compared to InAs S/D. A g<sub>m</sub> of 1310 μS/μm with an SS<sub>sat</sub> of 82mV/dec is achieved for an L<sub>g</sub>=46nm device. At this L<sub>g</sub>, a record I<sub>on</sub> above 200μA/μm is obtained at I<sub>off</sub> of 100nA/μm and V<sub>ds</sub>=0.5V on a 300mm Si platform.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"279 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm\",\"authors\":\"X. Zhou, N. Waldron, G. Boccardi, F. Sebaai, C. Merckling, G. Eneman, S. Sioncke, L. Nyns, A. Opdebeeck, J. Maes, Q. Xie, M. Givens, F. Tang, X. Jiang, W. Guo, B. Kunert, L. Teugels, K. Devriendt, A. S. Hernandez, J. Franco, D. V. van Dorp, K. Barla, N. Collaert, A. Thean\",\"doi\":\"10.1109/VLSIT.2016.7573420\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We report In<sub>0.53</sub>GaAs-channel gate-all-around FETs with channel width down to 7nm and L<sub>g</sub> down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak g<sub>m</sub> by 25% compared to InAs S/D. A g<sub>m</sub> of 1310 μS/μm with an SS<sub>sat</sub> of 82mV/dec is achieved for an L<sub>g</sub>=46nm device. At this L<sub>g</sub>, a record I<sub>on</sub> above 200μA/μm is obtained at I<sub>off</sub> of 100nA/μm and V<sub>ds</sub>=0.5V on a 300mm Si platform.\",\"PeriodicalId\":129300,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Technology\",\"volume\":\"279 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2016.7573420\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573420","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Scalability of InGaAs gate-all-around FET integrated on 300mm Si platform: Demonstration of channel width down to 7nm and Lg down to 36nm
We report In0.53GaAs-channel gate-all-around FETs with channel width down to 7nm and Lg down to 36nm, the smallest dimensions reported to date for IIIV devices fabricated on 300mm Si wafer. Furthermore, we systematically study the device scalability. InGaAs S/D improves the peak gm by 25% compared to InAs S/D. A gm of 1310 μS/μm with an SSsat of 82mV/dec is achieved for an Lg=46nm device. At this Lg, a record Ion above 200μA/μm is obtained at Ioff of 100nA/μm and Vds=0.5V on a 300mm Si platform.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
