High-density user-programmable logic array based on adjacent integration of pure-CMOS crossbar antifuse into logic CMOS circuits

Novel crossbar antifuse for high-density user programmable logic array (PLA) is presented. Circuit area reduction and routability increase of PLA are achieved by crossbar architecture based on pure-CMOS antifuse adjacently integrated into low-voltage and high-speed logic transistors. In addition, since our crossbar antifuse technique can be fabricated according to the standard design rule of advanced CMOS process, it is easy to implement our PLA as a user-customizable embedded logic in SoC. The logic density of our test chip in 65 nm process technology is 1835 lookup-tables (LUTs)/mm2, which is larger than any previous reports.