K. Nii, M. Yabuuchi, Y. Ishii, Miki Tanaka, M. Igarashi, K. Fukuoka, S. Tanaka
{"title":"先进汽车信息娱乐soc中用于DVFS和AVS的动态/静态SRAM电源管理方案","authors":"K. Nii, M. Yabuuchi, Y. Ishii, Miki Tanaka, M. Igarashi, K. Fukuoka, S. Tanaka","doi":"10.1109/VLSIT.2016.7573395","DOIUrl":null,"url":null,"abstract":"An embedded SRAM power management scheme using 16 nm FinFET technology is demonstrated in automotive infotainment SoCs. By introducing write-assist circuit technique, SRAM can operate down to 0.5 V wide voltage range, achieving DVFS for efficient power saving. Fast resume standby mode is also developed for reducing the leakage power of L1 cache under 2 GHz CPU operation. We confirmed that proposed thermal control scheme can be protected by thermal runaway failure.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"136 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A dynamic/static SRAM power management scheme for DVFS and AVS in advanced automotive infotainment SoCs\",\"authors\":\"K. Nii, M. Yabuuchi, Y. Ishii, Miki Tanaka, M. Igarashi, K. Fukuoka, S. Tanaka\",\"doi\":\"10.1109/VLSIT.2016.7573395\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An embedded SRAM power management scheme using 16 nm FinFET technology is demonstrated in automotive infotainment SoCs. By introducing write-assist circuit technique, SRAM can operate down to 0.5 V wide voltage range, achieving DVFS for efficient power saving. Fast resume standby mode is also developed for reducing the leakage power of L1 cache under 2 GHz CPU operation. We confirmed that proposed thermal control scheme can be protected by thermal runaway failure.\",\"PeriodicalId\":129300,\"journal\":{\"name\":\"2016 IEEE Symposium on VLSI Technology\",\"volume\":\"136 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Symposium on VLSI Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2016.7573395\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573395","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A dynamic/static SRAM power management scheme for DVFS and AVS in advanced automotive infotainment SoCs
An embedded SRAM power management scheme using 16 nm FinFET technology is demonstrated in automotive infotainment SoCs. By introducing write-assist circuit technique, SRAM can operate down to 0.5 V wide voltage range, achieving DVFS for efficient power saving. Fast resume standby mode is also developed for reducing the leakage power of L1 cache under 2 GHz CPU operation. We confirmed that proposed thermal control scheme can be protected by thermal runaway failure.
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