S. Ramesh, T. Ivanov, E. Camerotto, N. Sun, J. Franco, A. Sibaja-Hernandez, R. Rooyackers, A. Alian, J. Loo, A. Veloso, A. Milenin, D. Lin, P. Favia, H. Bender, N. Collaert, A. Thean, K. De Meyer
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引用次数: 7
Abstract
Vertical nanowires and for the first time vertical fins, dry etched from the same lattice matched InGaAs on InP, are used to fabricate MOSFETs. Single and multiple pillar array devices exhibit excellent electrostatics with min SS = 68mV/dec (VDS=0.05V) and max Gm = 580μS/μm (VDS=0.4V). These are the first III-V pillar array devices fabricated with top-down approach. Linear Ion scaling with effective width and overall Vth uniformity makes this result the first step in assessing the manufacturability of this integration scheme. A reliability analysis puts these vertical MOSFETs in line with other IIIV devices with similar gate stack, indicating that the IIIV etch does not introduce additional interface defects.
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