L. Brunet, P. Batude, C. Fenouillet-Béranger, P. Besombes, L. Hortemel, F. Ponthenier, B. Previtali, C. Tabone, A. Royer, C. Agraffeil, C. Euvrard-Colnat, A. Seignard, C. Morales, F. Fournel, L. Benaissa, T. Signamarcheix, P. Besson, M. Jourdan, R. Kachtouli, V. Benevent, J. Hartmann, C. Comboroure, N. Allouti, N. Possémé, C. Vizioz, C. Arvet, S. Barnola, S. Kerdilès, L. Baud, L. Pasini, C-M. V. Lu, F. Deprat, A. Toffoli, G. Romano, C. Guedj, V. Delaye, F. Boeuf, O. Faynot, M. Vinet
{"title":"First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers","authors":"L. Brunet, P. Batude, C. Fenouillet-Béranger, P. Besombes, L. Hortemel, F. Ponthenier, B. Previtali, C. Tabone, A. Royer, C. Agraffeil, C. Euvrard-Colnat, A. Seignard, C. Morales, F. Fournel, L. Benaissa, T. Signamarcheix, P. Besson, M. Jourdan, R. Kachtouli, V. Benevent, J. Hartmann, C. Comboroure, N. Allouti, N. Possémé, C. Vizioz, C. Arvet, S. Barnola, S. Kerdilès, L. Baud, L. Pasini, C-M. V. Lu, F. Deprat, A. Toffoli, G. Romano, C. Guedj, V. Delaye, F. Boeuf, O. Faynot, M. Vinet","doi":"10.1109/VLSIT.2016.7573428","DOIUrl":null,"url":null,"abstract":"For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.","PeriodicalId":129300,"journal":{"name":"2016 IEEE Symposium on VLSI Technology","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"58","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Symposium on VLSI Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2016.7573428","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 58
Abstract
For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.
首次展示了基于CMOS的全3D CMOS CoolCube™集成,其顶级兼容最先进的高性能FDSOI(全耗尽硅绝缘体)工艺要求,如高k/金属栅极或提高源极和漏极。功能3D逆变器与PMOS或NMOS在顶层突出显示。此外,介绍了工业短回路28nm W Metal 1级以上的Si层转移和前端环境中的返回,确认了CoolCube™集成的工业兼容性。