L. Pasini, P. Batude, J. Lacord, M. Cassé, B. Mathieu, B. Sklénard, F. P. Luce, J. Micout, A. Payet, F. Mazen, P. Besson, E. Ghegin, J. Borrel, R. Daubriac, L. Hutin, D. Blachier, D. Barge, S. Chhun, V. Mazzocchi, A. Cros, J. Barnes, Z. Saghi, V. Delaye, N. Rambal, V. Lapras, J. Mazurier, O. Weber, F. Andrieu, L. Brunet, C. Fenouillet-Béranger, Q. Rafhay, G. Ghibaudo, F. Cristiano, M. Haond, F. Boeuf, M. Vinet
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High performance CMOS FDSOI devices activated at low temperature
3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).
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